Patents by Inventor Katsuya Fukase

Katsuya Fukase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150009645
    Abstract: A wiring substrate includes an insulating layer that is an outermost layer of the wiring substrate and includes an external exposed surface, a pad forming part formed on a side of the external exposed surface, and a pad that projects from the external exposed surface. The pad forming part includes a recess part recessed from the external exposed surface, and a weir part that projects from the external exposed surface and encompasses the recess part from a plan view. The pad includes a pad body formed within the recess part and the weir part, and an eave part formed on the weir part. The pad body includes an end part that projects to the weir part. The eave part projects in a horizontal direction from the end part of the pad body. The end part of the pad body includes a flat surface.
    Type: Application
    Filed: June 19, 2014
    Publication date: January 8, 2015
    Inventors: Kentaro KANEKO, Katsuya FUKASE
  • Publication number: 20150008020
    Abstract: A wiring board includes a first wiring layer including a first conductive layer and a second conductive layer coating a first surface and a side surface of the first conductive layer. A first insulating layer covers a first surface and a side surface of the second conductive layer so as to expose a second surface of the first conductive layer opposite to the first surface of the first conductive layer. A second wiring layer is stacked on a first surface of the first insulating layer and is electrically connected to the first wiring layer. The first surface and the side surface of the first conductive layer are smooth surfaces while the first surface and the side surface of the second conductive layer are roughened-surfaces.
    Type: Application
    Filed: June 20, 2014
    Publication date: January 8, 2015
    Inventors: Kentaro KANEKO, Katsuya FUKASE
  • Publication number: 20140360765
    Abstract: A wiring substrate includes a core, first and second wiring layers formed on opposite sides of the core, an electronic component arranged in a cavity of the core, and a first insulating layer that fills the cavity and covers the one surface of the core. The electronic component is partially buried in the first insulating layer and partially projected from the cavity and exposed from the first insulating layer. A second insulating layer covers the first insulating layer. A third insulating layer covers the core and the projected and exposed portion of the electronic component. The thickness of the third insulating layer where the first wiring layer is located is equal to the total thickness of the first insulating layer and the second insulating layer where the second wiring layer is located.
    Type: Application
    Filed: May 30, 2014
    Publication date: December 11, 2014
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Takayuki KIWANAMI, Junji SATO, Katsuya FUKASE
  • Publication number: 20140360760
    Abstract: A wiring substrate includes a core, a first wiring layer formed on a first surface of the core, a second wiring layer formed on a second surface of the core, and an electronic component partially accommodated in the cavity and including a projected portion projected from the first opening of the core. A first insulating layer covers a side surface of the electronic component and the first surface of the core and fills a portion of the cavity. A second insulating layer covers the first insulating layer. A third insulating layer covers the second surface of the core. The remainder of the cavity that is not filled with the first insulating layer is filled with the third insulating layer.
    Type: Application
    Filed: June 4, 2014
    Publication date: December 11, 2014
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Takayuki KIWANAMI, Junji SATO, Katsuya FUKASE
  • Patent number: 8186053
    Abstract: A circuit board has plated through holes which are laid out with a fine pitch and meets requirements relating to characteristics such as strength and thermal expansion coefficient. A method of manufacturing a circuit board includes: a step of forming a core portion by thermal compression bonding prepregs formed by disposing carbon fibers so as to produce openings at positions where plated through holes will pass through and impregnating the carbon fibers with resin; a step of forming through holes that pass inside the openings at positions of the openings in the core portion; and a step of forming a conductive layer on inner surfaces of the through holes to form plated through holes at positions that do not interfere with the carbon fibers and thereby produce a core substrate.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: May 29, 2012
    Assignees: Fujitsu Limited, Shinko Electric Industries Co., Ltd.
    Inventors: Kishio Yokouchi, Hideaki Yoshimura, Katsuya Fukase
  • Patent number: 8166648
    Abstract: There is provided a wiring substrate manufacturing method. The wiring substrate includes: a plurality of conductor patterns formed on a mounting surface on which an electronic component is to be mounted, wherein each of the conductor patterns is covered with a corresponding one of solder layers; and partition walls made of insulating material and formed along the conductor patterns on the mounting surface such that each of the partition walls is provided between the adjacent conductor patterns with a clearance interposed therebetween.
    Type: Grant
    Filed: March 2, 2009
    Date of Patent: May 1, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Katsuya Fukase
  • Patent number: 8161636
    Abstract: A circuit board has plated through holes which are laid out with a fine pitch and meets requirements relating to characteristics such as the thermal expansion coefficient of the circuit board. A method of manufacturing a circuit board includes: a step of forming a core portion by thermal compression bonding prepregs which include first fibers that conduct electricity and second fibers that do not conduct electricity, which have the second fibers disposed at positions where plated through holes will pass through, and which are impregnated with resin; a step of forming through holes at positions in the core portion where the second fibers are disposed; and a step of forming a conductive layer on inner surfaces of the through holes to form plated through holes at positions that do not interfere with the first fibers and thereby produce a core substrate.
    Type: Grant
    Filed: November 17, 2008
    Date of Patent: April 24, 2012
    Assignees: Fujitsu Limited, Shinko Electric Industries Co., Ltd.
    Inventors: Kishio Yokouchi, Hideaki Yoshimura, Katsuya Fukase
  • Patent number: 8143533
    Abstract: There are provided a method for forming a resist pattern for preparing a circuit board having a landless or small-land-width through-hole(s) to realize a high-density circuit board, a method for producing a circuit board, and a circuit board. A method for forming a resist pattern, comprising the steps of forming a resin layer and a mask layer on a first surface of a substrate having a through-hole(s), and removing the resin layer on the through-hole(s) and on a periphery of the through-hole(s) on the first surface by supplying a resin layer removing solution from a second surface opposite to the first surface of the substrate, and a method for producing a circuit board using the method for forming a resist pattern, and a circuit board.
    Type: Grant
    Filed: May 17, 2006
    Date of Patent: March 27, 2012
    Assignees: Mitsubishi Paper Mills Limited, Shinko Electric Industries Co., Ltd.
    Inventors: Yasuo Kaneda, Munetoshi Irisawa, Yuji Toyoda, Toyokazu Komuro, Katsuya Fukase, Toyoaki Sakai
  • Patent number: 8066862
    Abstract: A manufacturing method of a wiring board includes a sticking layer forming step; a resist film forming step of forming a resist film on an upper surface of the sticking layer, the resist film having an opening exposing the upper surface of the sticking layer; a metal layer forming step of forming a metal layer, so as to cover an upper surface of the resist film and cover a side surface of the resist film and the upper surface of the sticking layer forming the opening for forming the wiring; a plating film forming step of filling with a plating film the opening for forming the wiring; a metal layer and plating film removing step; a resist film removing step; and a sticking layer removing step of removing the sticking layer of an unnecessary part not covered with the metal layer, after the resist film removing step.
    Type: Grant
    Filed: November 28, 2008
    Date of Patent: November 29, 2011
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Tomoo Yamasaki, Katsuya Fukase
  • Patent number: 7999193
    Abstract: There is provided a wiring substrate. The wiring substrate includes: a core substrate formed of a conductive material and having a through hole therein; an insulating layer formed on first and second surfaces of the core substrate; wiring patterns formed on the first and second surfaces via the insulating layer; and a via formed in the through hole and electrically connected to the wiring patterns. The via includes: a conductor ball and a conductor portion. The conductor ball has a conductive surface and an insulating member covering the conductive surface. A portion of the conductive surface is exposed from the insulating member. The conductor portion is electrically connected to the exposed conductive surface and the wiring patterns. At least one of the insulating member and the insulating layer is interposed between the via and the core substrate.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: August 16, 2011
    Assignees: Shinko Electric Industries, Co., Ltd., Fujitsu Limited
    Inventors: Katsuya Fukase, Kishio Yokouchi, Hideaki Yoshimura
  • Publication number: 20100122843
    Abstract: A circuit board has plated through holes which are laid out with a fine pitch and meets requirements relating to characteristics such as strength and thermal expansion coefficient. A method of manufacturing a circuit board includes: a step of forming a core portion by thermal compression bonding prepregs formed by disposing carbon fibers so as to produce openings at positions where plated through holes will pass through and impregnating the carbon fibers with resin; a step of forming through holes that pass inside the openings at positions of the openings in the core portion; and a step of forming a conductive layer on inner surfaces of the through holes to form plated through holes at positions that do not interfere with the carbon fibers and thereby produce a core substrate.
    Type: Application
    Filed: November 14, 2008
    Publication date: May 20, 2010
    Applicants: FUJITSU LIMITED, SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Kishio YOKOUCHI, Hideaki YOSHIMURA, Katsuya FUKASE
  • Patent number: 7679004
    Abstract: As means for solving a problem of a positional shift of a land and a hole which is caused by an alignment in the formation of an etching resist layer and a plated resist layer in a method of manufacturing a circuit board, there are provided a method of manufacturing a circuit board including the steps of forming a first resin layer on a surface of an insulating substrate having a conductive layer on the surface and an internal wall of a through hole or/and a non-through hole, forming a second resin layer which is insoluble or slightly soluble in a developing solution for the first resin layer on the first resin layer provided on the surface conductive layer, and removing the first resin layer provided over the hole with the developing solution for the first resin layer, and a method of manufacturing a circuit board including the step of uniformly charging a surface of the first resin layer to induce a potential difference to the first resin layer provided over the hole and the first resin layer provided on th
    Type: Grant
    Filed: March 2, 2005
    Date of Patent: March 16, 2010
    Assignees: Shinko Electric Industries Co., Ltd., Mitsubishi Paper Mills Limited
    Inventors: Katsuya Fukase, Toyoaki Sakai, Munetoshi Irisawa, Toyokazu Komuro, Yasuo Kaneda, Masanori Natsuka, Wakana Aizawa
  • Publication number: 20090236137
    Abstract: There are provided a method for forming a resist pattern for preparing a circuit board having a landless or small-land-width through-hole(s) to realize a high-density circuit board, a method for producing a circuit board, and a circuit board. A method for forming a resist pattern, comprising the steps of forming a resin layer and a mask layer on a first surface of a substrate having a through-hole(s), and removing the resin layer on the through-hole(s) and on a periphery of the through-hole(s) on the first surface by supplying a resin layer removing solution from a second surface opposite to the first surface of the substrate, and a method for producing a circuit board using the method for forming a resist pattern, and a circuit board.
    Type: Application
    Filed: May 17, 2006
    Publication date: September 24, 2009
    Inventors: Yasuo Kaneda, Munetoshi Irisawa, Yuji Toyoda, Toyokazu Komuro, Katsuya Fukase, Toyoaki Sakai
  • Publication number: 20090218122
    Abstract: There is provided a wiring substrate. The wiring substrate includes: a plurality of conductor patterns formed on a mounting surface on which an electronic component is to be mounted, wherein each of the conductor patterns is covered with a corresponding one of solder layers; and partition walls made of insulating material and formed along the conductor patterns on the mounting surface such that each of the partition walls is provided between the adjacent conductor patterns with a clearance interposed therebetween.
    Type: Application
    Filed: March 2, 2009
    Publication date: September 3, 2009
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Katsuya Fukase
  • Publication number: 20090188806
    Abstract: A manufacturing method of a wiring board includes a sticking layer forming step; a resist film forming step of forming a resist film on an upper surface of the sticking layer, the resist film having an opening exposing the upper surface of the sticking layer; a metal layer forming step of forming a metal layer, so as to cover an upper surface of the resist film and cover a side surface of the resist film and the upper surface of the sticking layer forming the opening for forming the wiring; a plating film forming step of filling with a plating film the opening for forming the wiring; a metal layer and plating film removing step; a resist film removing step; and a sticking layer removing step of removing the sticking layer of an unnecessary part not covered with the metal layer, after the resist film removing step.
    Type: Application
    Filed: November 28, 2008
    Publication date: July 30, 2009
    Inventors: Tomoo Yamasaki, Katsuya Fukase
  • Publication number: 20090095521
    Abstract: A circuit board has plated through holes which are laid out with a fine pitch and meets requirements relating to characteristics such as the thermal expansion coefficient of the circuit board. A method of manufacturing a circuit board includes: a step of forming a core portion by thermal compression bonding prepregs which include first fibers that conduct electricity and second fibers that do not conduct electricity, which have the second fibers disposed at positions where plated through holes will pass through, and which are impregnated with resin; a step of forming through holes at positions in the core portion where the second fibers are disposed; and a step of forming a conductive layer on inner surfaces of the through holes to form plated through holes at positions that do not interfere with the first fibers and thereby produce a core substrate.
    Type: Application
    Filed: November 17, 2008
    Publication date: April 16, 2009
    Applicants: FUJITSU LIMITED, SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Kishio YOKOUCHI, Hideaki YOSHIMURA, Katsuya FUKASE
  • Publication number: 20090095520
    Abstract: There is provided a wiring substrate. The wiring substrate includes: a core substrate formed of a conductive material and having a through hole therein; an insulating layer formed on first and second surfaces of the core substrate; wiring patterns formed on the first and second surfaces via the insulating layer; and a via formed in the through hole and electrically connected to the wiring patterns. The via includes: a conductor ball and a conductor portion. The conductor ball has a conductive surface and an insulating member covering the conductive surface. A portion of the conductive surface is exposed from the insulating member. The conductor portion is electrically connected to the exposed conductive surface and the wiring patterns. At least one of the insulating member and the insulating layer is interposed between the via and the core substrate.
    Type: Application
    Filed: October 8, 2008
    Publication date: April 16, 2009
    Applicants: SHINKO ELECTRIC INDUSTRIES CO., LTD., FUJITSU LIMITED
    Inventors: Katsuya Fukase, Kishio Yokouchi, Hideaki Yoshimura
  • Patent number: 7454832
    Abstract: A method of forming a high aspect ratio metal plate pattern or circuit board by multi-stage etching with a metal mask is disclosed. A resist (12) is coated on one or two surfaces of a copper plate (10) and patterned into a resist pattern. A tin plating layer (14) is formed using this resist pattern, and with this tin plating layer as a mask, the copper plate is half etched. By coating, exposing and developing the positive resist (18), the positive resist under the tin plating layer is protected. With the tin plating layer and the protective resist layer as a mask, the half etching is executed again. This process is repeated until the resist and the tin plating layer used as a masking are finally removed to produce a metal pattern (20).
    Type: Grant
    Filed: August 18, 2006
    Date of Patent: November 25, 2008
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Toyoaki Sakai, Katsuya Fukase
  • Patent number: 7415762
    Abstract: An interposer to be interposed between a semiconductor chip to be mounted thereon and a packaging board has an interposer portion made of a semiconductor and an interposer portion provided around the foregoing interposer portion integrally therewith. On both surfaces of the interposer portions, wiring patterns are formed via insulating layers. The wiring patterns are electrically connected via through holes formed at required positions in the interposer portions. The outer interposer portion is made of an insulator or a metal body. Further, external connection terminals are bonded to one surface of the interposer.
    Type: Grant
    Filed: July 19, 2006
    Date of Patent: August 26, 2008
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Katsuya Fukase, Shinichi Wakabayashi
  • Patent number: 7388293
    Abstract: An interposer to be interposed between a semiconductor chip to be mounted thereon and a packaging board has an interposer portion made of a semiconductor material and an interposer portion provided around the foregoing interposer portion integrally therewith. On both surfaces of the interposer portions, wiring patterns are formed via insulating layers. The wiring patterns are electrically connected via through holes formed at required positions in the interposer portions. The outer interposer portion is made of an insulator or a metal body. Further, external connection terminals are bonded to one surface of the interposer.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: June 17, 2008
    Assignee: Shinko Electric Industries, Co.
    Inventors: Katsuya Fukase, Shinichi Wakabayashi