Patents by Inventor Katsuya Kikuchi

Katsuya Kikuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11270968
    Abstract: The purpose of the present invention is to provide an electronic circuit connection method and an electronic circuit capable of improving the reliability of electrical connection. A connection method for an electronic circuit 100 includes: a process of forming a first metal bumps 30 and a second metal bump 40, each of which has a cone shape; and a process of joining a first electrode pad 12 and a third electrode pad 22 by the first metal bump 30 and joining a second electrode pad 13 and a fourth electrode pad 23 by the second metal bump 40, wherein at least one region of between a first region 11a and a second region 11b in a first connection surface 11 and between a third region 21a and a fourth region 21b in a second connection surface 21 has a step 11c, and the first metal bump 30 and the second metal bump 40 have different heights so as to correct a height H1 of the step 11c.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: March 8, 2022
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Masaru Hashino, Ying Ying Lim, Hiroshi Nakagawa, Masahiro Aoyagi, Katsuya Kikuchi
  • Publication number: 20210249374
    Abstract: The purpose of the present invention is to provide an electronic circuit connection method and an electronic circuit capable of improving the reliability of electrical connection. A connection method for an electronic circuit 100 includes: a process of forming a first metal bumps 30 and a second metal bump 40, each of which has a cone shape; and a process of joining a first electrode pad 12 and a third electrode pad 22 by the first metal bump 30 and joining a second electrode pad 13 and a fourth electrode pad 23 by the second metal bump 40, wherein at least one region of between a first region 11a and a second region 11b in a first connection surface 11 and between a third region 21a and a fourth region 21b in a second connection surface 21 has a step 11c, and the first metal bump 30 and the second metal bump 40 have different heights so as to correct a height H1 of the step 11c.
    Type: Application
    Filed: May 30, 2019
    Publication date: August 12, 2021
    Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Masaru HASHINO, Ying Ying LIM, Hiroshi NAKAGAWA, Masahiro AOYAGI, Katsuya KIKUCHI
  • Patent number: 9984956
    Abstract: Provided are a through electrode including an organic side-wall insulating film, capable of eliminating a barrier layer and achieving satisfactory mechanical reliability and electrical reliability and a manufacturing method thereof, and a semiconductor device and a manufacturing method thereof. According to one aspect of the present invention, a through electrode disposed in a semiconductor substrate is provided, including: a copper layer in the semiconductor substrate; and a side-wall insulating film that is disposed between the copper layer and the semiconductor substrate so as to be in contact with the copper layer and the semiconductor substrate, the side-wall insulating film being represented by the following chemical formula (1).
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: May 29, 2018
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Masahiro Aoyagi, Tung Thanh Bui, Naoya Watanabe, Fumiki Kato, Katsuya Kikuchi
  • Patent number: 9818645
    Abstract: Embodiments provided are a through electrode that can be manufactured by a method not including the step of removing a side-wall insulating film formed at the bottom part of the through hole and so having improved electrical characteristics and mechanical reliability and a manufacturing method thereof as well as a semiconductor device and a manufacturing method thereof. A through electrode is disposed in a semiconductor substrate, and includes: a conductive layer; a side-wall insulating film that is disposed between the conductive layer and the semiconductor substrate, the side-wall insulating film being represented by the following chemical formula (1), and a tubular semiconductor layer disposed between the conductive layer and the semiconductor substrate, the semiconductor layer including a same material as the material of the semiconductor substrate.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: November 14, 2017
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Masahiro Aoyagi, Tung Thanh Bui, Naoya Watanabe, Katsuya Kikuchi, Wei Feng
  • Publication number: 20170200644
    Abstract: Embodiments provided are a through electrode that can be manufactured by a method not including the step of removing a side-wall insulating film formed at the bottom part of the through hole and so having improved electrical characteristics and mechanical reliability and a manufacturing method thereof as well as a semiconductor device and a manufacturing method thereof. A through electrode is disposed in a semiconductor substrate, and includes: a conductive layer; a side-wall insulating film that is disposed between the conductive layer and the semiconductor substrate, the side-wall insulating film being represented by the following chemical formula (1), and a tubular semiconductor layer disposed between the conductive layer and the semiconductor substrate, the semiconductor layer including a same material as the material of the semiconductor substrate.
    Type: Application
    Filed: August 30, 2016
    Publication date: July 13, 2017
    Inventors: Masahiro AOYAGI, Tung Thanh BUI, Naoya WATANABE, Katsuya KIKUCHI, Wei FENG
  • Publication number: 20160322282
    Abstract: Provided are a through electrode including an organic side-wall insulating film, capable of eliminating a barrier layer and achieving satisfactory mechanical reliability and electrical reliability and a manufacturing method thereof, and a semiconductor device and a manufacturing method thereof. According to one aspect of the present invention, a through electrode disposed in a semiconductor substrate is provided, including: a copper layer in the semiconductor substrate; and a side-wall insulating film that is disposed between the copper layer and the semiconductor substrate so as to be in contact with the copper layer and the semiconductor substrate, the side-wall insulating film being represented by the following chemical formula (1).
    Type: Application
    Filed: October 30, 2015
    Publication date: November 3, 2016
    Inventors: Masahiro AOYAGI, Tung Thanh BUI, Naoya WATANABE, Fumiki KATO, Katsuya KIKUCHI
  • Patent number: 9345145
    Abstract: An electroless gold plating solution with which one or more openings formed in a resist overlying a substrate can be filled in a short time, the openings having a width on the order of micrometer, in particular, 100 ?m or smaller, in terms of the width of the exposed substrate area, and having a height of 3 ?m or larger. The electroless gold plating solution contains a deposition accelerator for deposition in fine areas, and a microfine pattern of 100 ?m or finer is formed therefrom.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: May 17, 2016
    Assignee: Kanto Kagaku Kabushiki Kaisha
    Inventors: Ryota Iwai, Tomoaki Tokuhisa, Masaru Kato, Tokihiko Yokoshima, Masahiro Aoyagi, Yasuhiro Yamaji, Katsuya Kikuchi, Hiroshi Nakagawa
  • Patent number: 9134346
    Abstract: A method of making a contact probe including a step of making a first printed wiring board having a signal electrode and a ground electrode used as a contact part of the contact probe with respect to a measuring object, in which the signal electrode and ground electrode are formed of a metal wiring pattern, and making a second printed wiring board with a coaxial line structure having a shield electrode which encloses a signal line and the surroundings of the signal line through an insulating layer. The signal electrode of the first printed wiring board and the signal line of the second printed wiring board are electrically connected together, and the ground electrode of the first printed wiring board and the shield electrode of the second printed wiring board are electrically connected together.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: September 15, 2015
    Assignees: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, KIYOTO MANUFACTURING CO.
    Inventors: Masahiro Aoyagi, Katsuya Kikuchi, Hiroshi Nakagawa, Yoshikuni Okada, Hiroyuki Fujita, Shouichi Imai, Shigeo Kiyota
  • Patent number: 8399979
    Abstract: An electrode connection structure of a semiconductor chip is provided to realize a highly reliable electrical connection with low stress without using a bump. A conductive member may be used for such an electrode connection structure. A semiconductor device is provided wherein semiconductor chips are arranged in layers without providing the semiconductor chips with a through via, and a method is provided for manufacturing such a semiconductor device. A part or all of the surface of a horizontal recess, which is formed in an adhesive layer arranged between a first electrode of a lower layer and a second electrode of an upper layer, is provided with a conductive member for connecting the first electrode and the second electrode.
    Type: Grant
    Filed: July 6, 2007
    Date of Patent: March 19, 2013
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Yasuhiro Yamaji, Tokihiko Yokoshima, Masahiro Aoyagi, Hiroshi Nakagawa, Katsuya Kikuchi
  • Patent number: 8367468
    Abstract: An electrode connection structure of a semiconductor chip is provided to realize a highly reliable electrical connection with low stress without using a bump. A conductive member may be used for such an electrode connection structure. A semiconductor device is provided wherein semiconductor chips are arranged in layers without providing the semiconductor chips with a through via, and a method is provided for manufacturing such a semiconductor device. A part or all of the surface of a horizontal recess, which is formed in an adhesive layer arranged between a first electrode of a lower layer and a second electrode of an upper layer, is provided with a conductive member for connecting the first electrode and the second electrode.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: February 5, 2013
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Yasuhiro Yamaji, Tokihiko Yokoshima, Masahiro Aoyagi, Hiroshi Nakagawa, Katsuya Kikuchi
  • Publication number: 20120119352
    Abstract: An electroless gold plating solution with which one or more openings formed in a resist overlying a substrate can be filled in a short time, the openings having a width on the order of micrometer, in particular, 100 ?m or smaller, in terms of the width of the exposed substrate area, and having a height of 3 ?m or larger. The electroless gold plating solution contains a deposition accelerator for deposition in fine areas, and a microfine pattern of 100 ?m or finer is formed therefrom.
    Type: Application
    Filed: March 10, 2010
    Publication date: May 17, 2012
    Applicant: Kanto Kagaku Kabushiki Kaisha
    Inventors: Ryota Iwai, Tomoaki Tokuhisa, Masaru Kato, Tokihiro Yokoshima, Masahiro Aoyagi, Yasuhiro Yamaji, Katsuya Kikuchi, Hiroshi Nakagawa
  • Publication number: 20120108008
    Abstract: An electrode connection structure of a semiconductor chip is provided to realize a highly reliable electrical connection with low stress without using a bump. A conductive member may be used for such an electrode connection structure. A semiconductor device is provided wherein semiconductor chips are arranged in layers without providing the semiconductor chips with a through via, and a method is provided for manufacturing such a semiconductor device. A part or all of the surface of a horizontal recess, which is formed in an adhesive layer arranged between a first electrode of a lower layer and a second electrode of an upper layer, is provided with a conductive member for connecting the first electrode and the second electrode.
    Type: Application
    Filed: April 28, 2011
    Publication date: May 3, 2012
    Applicant: National Institute of Advanced Industrial Science and Technology
    Inventors: Yasuhiro Yamaji, Tokihiko Yokoshima, Masahiro Aoyagi, Hiroshi Nakagawa, Katsuya Kikuchi
  • Publication number: 20110247209
    Abstract: [Problem] To provide a contact probe which can easily be connected with a measurement apparatus electrically, can measure a high speed and high frequency signal with a fine pitch easily and correctly, and can easily cope with signal measurement for a plurality of channels, and a method of making the contact probe. [Means to Solve Problem] It includes a first printed wiring board 3 having a signal electrode 10a and a ground electrode 10b used as a contact part with respect to a measuring object, in which the signal electrode 10a and ground electrode 10b are formed of a metal wiring pattern on a substrate, and a second printed wiring board 2 with a coaxial line structure having shield electrodes 12, 17, 18 which enclose a signal line 15a and the surroundings of the signal line 15a through an insulating layer.
    Type: Application
    Filed: June 24, 2011
    Publication date: October 13, 2011
    Applicants: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, KIYOTA MANUFACTURING CO., TSS CORPORATION
    Inventors: Masahiro Aoyagi, Katsuya Kikuchi, Hiroshi Nakagawa, Yoshikuni Okada, Hiroyuki Fujita, Shouichi Imai, Shigeo Kiyota
  • Patent number: 7990165
    Abstract: To provide a contact probe which can easily be connected with a measurement apparatus electrically, can measure a high speed and high frequency signal with a fine pitch easily and correctly, and can easily cope with signal measurement for a plurality of channels, and a method of making the contact probe. It includes a first printed wiring board 3 having a signal electrode 10a and a ground electrode 10b used as a contact part with respect to a measuring object, in which the signal electrode 10a and ground electrode 10b are formed of a metal wiring pattern on a substrate, and a second printed wiring board 2 with a coaxial line structure having shield electrodes 12, 17, 18 which enclose a signal line 15a and the surroundings of the signal line 15a through an insulating layer.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: August 2, 2011
    Assignees: National Institute of Advanced Industrial Science and Technology, Kiyoto Manufacturing Co., TSS Corporation
    Inventors: Masahiro Aoyagi, Katsuya Kikuchi, Hiroshi Nakagawa, Yoshikuni Okada, Hiroyuki Fujita, Shoichi Imai, Shigeo Kiyota
  • Patent number: 7833835
    Abstract: An interposer having multi-layer fine wiring structure which comprises an insulating layer made of photosensitive polyimide which is photosensitive organic material and a wiring layer portion made of metal, such as copper, silver, gold, aluminum, palladium, indium, titanium, tantalum, and niobium, functions as wiring in an integrated circuit chip, wherein junctions between the integrated circuit chip and the interposer are formed by micron to submicron size fine connection metal pads or bumps which are formed on both the integrated circuit chip and the interposer.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: November 16, 2010
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Masahiro Aoyagi, Hiroshi Nakagawa, Kazuhiko Tokoro, Katsuya Kikuchi, Yoshikuni Okada
  • Patent number: 7787121
    Abstract: An imaging apparatus includes a light source unit that selectively outputs white light and light in a different wavelength band to an observation target, an imaging unit including an imaging device, and a spectral image formation circuit that generates a spectral image signal for a specified wavelength by an operation using an image signal based on an output from the imaging unit and predetermined matrix data. The imaging unit selectively obtains an image of the observation target for each of first, second and third light components in a visible light region and an image for each of at least fourth and fifth light components in a near-infrared region. Further, the imaging unit includes first spectral devices that make only the first and fourth light components enter first pixels of the imaging device and second spectral devices that make only the second and fifth light components enter second pixels thereof.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: August 31, 2010
    Assignees: FUJIFILM Corporation, Fujinon Corporation
    Inventors: Kazuhiro Tsujita, Hiroshi Sunagawa, Katsuya Kikuchi, Tetsuya Kawanishi
  • Patent number: 7767574
    Abstract: The present invention provides a method of forming a micro metal bump, which is capable of stably and industrially forming a micro metal bump, by a gas deposition process, at a prescribed position of a metal part formed on one side surface of a substrate.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: August 3, 2010
    Assignees: Kabushiki Kaisha Mikuni Kogyo, National Institute of Advanced Industrial Science and Technology
    Inventors: Yoshihiro Gomi, Masahiro Aoyagi, Hiroshi Nakagawa, Katsuya Kikuchi, Yoshikuni Okada, Hirotaka Oosato
  • Publication number: 20100044870
    Abstract: An electrode connection structure of a semiconductor chip is provided to realize a highly reliable electrical connection with low stress without using a bump. A conductive member may be used for such an electrode connection structure. A semiconductor device is provided wherein semiconductor chips are arranged in layers without providing the semiconductor chips with a through via, and a method is provided for manufacturing such a semiconductor device. A part or all of the surface of a horizontal recess, which is formed in an adhesive layer arranged between a first electrode of a lower layer and a second electrode of an upper layer, is provided with a conductive member for connecting the first electrode and the second electrode.
    Type: Application
    Filed: July 6, 2007
    Publication date: February 25, 2010
    Applicant: National Institute of Advanced Industrial Science and Technology
    Inventors: Yasuhiro Yamaji, Tokihiko Yokoshima, Masahiro Aoyagi, Hiroshi Nakagawa, Katsuya Kikuchi
  • Publication number: 20090224781
    Abstract: [Problem]To provide a contact probe which can easily be connected with a measurement apparatus electrically, can measure a high speed and high frequency signal with a fine pitch easily and correctly, and can easily cope with signal measurement for a plurality of channels, and a method of making the contact probe. [Means to Solve Problem] It includes a first printed wiring board 3 having a signal electrode 10a and a ground electrode 10b used as a contact part with respect to a measuring object, in which the signal electrode 10a and ground electrode 10b are formed of a metal wiring pattern on a substrate, and a second printed wiring board 2 with a coaxial line structure having shield electrodes 12, 17, 18 which enclose a signal line 15a and the surroundings of the signal line 15a through an insulating layer.
    Type: Application
    Filed: April 19, 2007
    Publication date: September 10, 2009
    Applicants: SHINWA FRONTECH CORP., KIYOTA MANUFACTURING CO.
    Inventors: Masahiro Aoyagi, Katsuya Kikuchi, Hiroshi Nakagawa, Yoshikuni Okada, Hiroyuki Fujita, Shouichi Imai, Shigeo Kiyota
  • Publication number: 20090104766
    Abstract: The present invention provides a method of forming a micro metal bump, which is capable of stably and industrially forming a micro metal bump, by a gas deposition process, at a prescribed position of a metal part formed on one side surface of a substrate.
    Type: Application
    Filed: March 30, 2007
    Publication date: April 23, 2009
    Inventors: Yoshihiro Gomi, Masahiro Aoyagi, Hiroshi Nakagawa, Katsuya Kikuchi, Yoshikuni Okada, Hirotaka Oosato