Patents by Inventor Katsuya Oda

Katsuya Oda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070197258
    Abstract: Up and down signal levels in a wireless base station and a forward base station can be automatically adjusted into predetermined levels respectively with a simple configuration. In an interface portion 12, a pilot signal P of a predetermined level is generated by a pilot signal generator 120, and multiplexed with a down transmission signal 111 from a wireless base station 11 by a multiplexer 121. The multiplexed signal is amplified with a constant gain by a down signal amplifier 122, then converted into a down optical signal by an electro-optic converter 123, wavelength-multiplexed by an optical multi/demultiplexer 124, sent out to an optical fiber 15, and transmitted to a forward base station 13. In the forward base station 13, the down optical signal wavelength-demultiplexed by an optical multi/demultiplexer 124 is converted into a down electric signal by an opto-electric converter 125, and the pilot signal P is demultiplexed by a demultiplexer 133.
    Type: Application
    Filed: June 2, 2005
    Publication date: August 23, 2007
    Applicant: Matsushita Electric Industrial Co., Ltd
    Inventors: Katsuya Oda, Hitomaro Tohgoh, Yoshiyasu Sato, Hiroaki Asano
  • Publication number: 20070178676
    Abstract: Disclosed herein is a method of forming a single crystal SiC on a Si Substrate wherein a SiGe layer lower in melting point than Si and SiC and an amorphous SiC are formed on the Si layer and this structure is annealed at a temperature higher than the melting point of SiGe to relieve strain between SiC and the Si substrate and to cause an amorphous SiC to crystallize at the same time, thereby forming the single crystal SiC layer good in crystallinity and surface morphology.
    Type: Application
    Filed: January 19, 2007
    Publication date: August 2, 2007
    Inventor: Katsuya Oda
  • Publication number: 20070064761
    Abstract: Optical transmission apparatus 100 is provided with laser element 101 and optical fiber 102 and has an optimum position where the efficiency of optical coupling between laser element 101 and optical fiber 102 becomes a maximum. Laser element 101 and optical fiber 102 are fixed at positions shifted from the optimum position in the direction of the optical axis by a value within a range from 10 ?m to 150 ?m. It is possible to construct the apparatus such that outgoing light of laser element 101 is not parallel to the optical axis of outgoing light from an end face of optical fiber 102 and the outgoing light of laser element 101 is not parallel to the optical axis of light reflected on the end face of optical fiber 102.
    Type: Application
    Filed: October 25, 2004
    Publication date: March 22, 2007
    Applicant: Matsushita Electric Industrial Co., LTD.
    Inventors: Hitomaro Togo, Katsuya Oda, Yoshiyasu Sato, Hiroaki Asano
  • Patent number: 7095043
    Abstract: An (SiGe)C layer having a stoichiometric ratio of about 1:1 is locally formed on an Si layer, a large forbidden band width semiconductor device is prepared inside the layered structure thereof and an Si semiconductor integrated circuit is formed in the regions not formed with the layered structure, whereby high frequency high power operation of the device is enabled by the large forbidden band width semiconductor device and high performance is attained by hybridization of the Si integrated circuit.
    Type: Grant
    Filed: March 2, 2004
    Date of Patent: August 22, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Katsuya Oda, Nobuyuki Sugii, Makoto Miura, Isao Suzumura, Katsuyoshi Washio
  • Publication number: 20060169987
    Abstract: A high quality silicon carbide (SiC) layer being substantially lower in threading dislocation density than a prior layer is formed on silicon (Si) substrate. A semiconductor device is fabricated in such a way that a semiconductor buffer layer containing Si in part and being higher in defect density than a Si substrate is formed on the Si substrate on the upper portion of which are formed a plurality of pairs of facets being mirror-symmetrical to the surface orientation of a semiconductor substrate, further on the top of the layer a SiC layer is sequentially formed.
    Type: Application
    Filed: March 7, 2005
    Publication date: August 3, 2006
    Inventors: Makoto Miura, Katsuya Oda, Katsuyoshi Washio
  • Publication number: 20060154450
    Abstract: A manufacturing method of a semiconductor device in which the oxygen and carbon concentrations are reduced at the interface of each layer making up the semiconductor multilayer film. A first semiconductor layer is formed on a single-crystal substrate in a first reactor; the substrate is transferred from the first reactor to a second reactor through a transfer chamber; and a second semiconductor layer is formed on the first semiconductor layer in the second reactor. During substrate transfer, hydrogen is supplied when the number of hydrogen atoms bonding with the surface atoms of the first semiconductor layer is less than the number of surface atoms of the first semiconductor layer, and the supply of hydrogen is stopped when the number of hydrogen atoms bonding with the surface atoms of the first semiconductor layer is greater than the number of surface atoms of the first semiconductor layer.
    Type: Application
    Filed: January 11, 2006
    Publication date: July 13, 2006
    Inventors: Isao Suzumura, Katsuya Oda
  • Patent number: 7052787
    Abstract: Proton-exchange membrane fuel-cell power generating equipment includes a heat exchanger coupled to a process burner and, therethrough, to a fan. When water needs to be heated, such as during startup, the water is circulated through the heat exchanger and the process burner is operated (ignited) to heat the water. When the water needs to be cooled, such as when a hot water reserving tank is full, the water is circulated through the heat exchanger and the fan is operated, but the process burner is not operated, to cool the water. Water is circulated through part or all of a water system to prevent freezing while the system is stopped. Optionally, the process burner is operated to heat the circulated water. The heat exchanger and other heat exchangers in the system are arranged to efficiently recover heat from burners, a fuel-cell cooling system and exothermic processes.
    Type: Grant
    Filed: January 9, 2002
    Date of Patent: May 30, 2006
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Osamu Tajima, Katsuya Oda, Tatsuji Hatayama, Ryuji Yukawa, Taketoshi Ouki, Akira Fuju, Koji Shindo, Kazuhiro Tajima, Satoshi Yamamoto, Katsuyuki Makihara, Keigo Miyai, Masataka Kadowaki, Masatoshi Ueda
  • Patent number: 6995054
    Abstract: A semiconductor device having an MODFET and at least one other device formed on one identical semiconductor substrate, in which an intrinsic region for the MODFET is formed by selective growth in a groove formed on a semiconductor substrate having an insulation film on the side wall of the groove, and single-crystal silicon at the bottom of the groove, is disclosed. The step between the MODFET and the at least one other device mounted together on one identical substrate can be thereby decreased, and each of the devices can be reduced in the size and integrated to a high degree, and the interconnection length can be shortened to reduce power consumption.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: February 7, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Katsuya Oda, Katsuyoshi Washio
  • Patent number: 6974977
    Abstract: A bipolar transistor is provided which is of high reliability and high gain, and which is particularly suitable to high speed operation. The bipolar transistor operates with high accuracy and with no substantial change of collector current even upon change of collector voltage. It also has less variation than conventional bipolar transistors for the collector current while ensuring high speed properties and high gain. In one example, the band gap in the base region is smaller than the band gap in the emitter and collector regions. The band gap is constant near the junction with the emitter region and decreases toward the junction with the collector region. A single crystal silicon/germanium is a typically used for the base region.
    Type: Grant
    Filed: June 10, 2003
    Date of Patent: December 13, 2005
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Katsuyoshi Washio, Reiko Hayami, Hiromi Shimamoto, Masao Kondo, Katsuya Oda, Eiji Oue, Masamichi Tanabe
  • Patent number: 6905972
    Abstract: A method of manufacturing a semiconductor device comprising a plurality of single-crystal semiconductor layers formed, for example, in an opening of an insulating film, said semiconductor layers having no or very few crystal defects. The method comprises forming in a first growth chamber a first semiconductor layer of a first conductivity type in an opening of an insulating film and subsequently forming in a second growth chamber a second semiconductor layer of a second conductivity type in an opening of an insulating film, while supplying hydrogen to the surface of the substrate when the substrate is transferred from said first growth chamber to said second growth chamber.
    Type: Grant
    Filed: May 21, 2002
    Date of Patent: June 14, 2005
    Assignee: Renesas Technology Corporation
    Inventor: Katsuya Oda
  • Publication number: 20050001238
    Abstract: A bipolar transistor is provided in which both the base resistance and the base-collector capacitance are reduced and which is capable of operating at a high cutoff frequency. The semiconductor device is structured so that the emitter and extrinsic base are separated from each other by an insulator sidewall and the bottom faces of the insulator sidewall, and the emitter are approximately on the same plane. The extrinsic base electrode and the collector region are separated from each other by an insulator.
    Type: Application
    Filed: May 28, 2004
    Publication date: January 6, 2005
    Inventors: Eiji Oue, Katsuyoshi Washio, Hiromi Shimamoto, Katsuya Oda, Makoto Miura
  • Publication number: 20040256613
    Abstract: An (SiGe)C layer having a stoichiometric ratio of about 1:1 is locally formed on an Si layer, a large forbidden band width semiconductor device is prepared inside the layered structure thereof and an Si semiconductor integrated circuit is formed in the regions not formed with the layered structure, whereby high frequency high power operation of the device is enabled by the large forbidden band width semiconductor device and high performance is attained by hybridization of the Si integrated circuit.
    Type: Application
    Filed: March 2, 2004
    Publication date: December 23, 2004
    Inventors: Katsuya Oda, Nobuyuki Sugii, Makoto Miura, Isao Suzumura, Katsuyoshi Washio
  • Publication number: 20040129982
    Abstract: A semiconductor device having an MODFET and at least one other device formed on one identical semiconductor substrate, in which an intrinsic region for the MODFET is formed by selective growth in a groove formed on a semiconductor substrate having an insulation film on the side wall of the groove, and single-crystal silicon at the bottom of the groove, is disclosed. The step between the MODFET and the at least one other device mounted together on one identical substrate can be thereby decreased, and each of the devices can be reduced in the size and integrated to a high degree, and the interconnection length can be shortened to reduce power consumption.
    Type: Application
    Filed: December 18, 2003
    Publication date: July 8, 2004
    Applicant: Renesas Technology Corporation
    Inventors: Katsuya Oda, Katsuyoshi Washio
  • Patent number: 6724019
    Abstract: A semiconductor device having an MODFET and at least one other device formed on one identical semiconductor substrate, in which an intrinsic region for the MODFET is formed by selective growth in a groove formed on a semiconductor substrate having an insulation film on the side wall of the groove, and single-crystal silicon at the bottom of the groove, is disclosed. The step between the MODFET and the at least one other device mounted together on one identical substrate can be thereby decreased, and each of the devices can be reduced in the size and integrated to a high degree, and the interconnection length can be shortened to reduce power consumption.
    Type: Grant
    Filed: April 3, 2001
    Date of Patent: April 20, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Katsuya Oda, Katsuyoshi Washio
  • Patent number: 6667489
    Abstract: A high-speed heterojunction bipolar transistor in a large injection of electrons from the emitter and a method for production thereof. In a typical example of the SiGeC heterojunction bipolar transistor, the collector has a layer of n-type single-crystal Si and a layer of n-type single-crystal SiGe, the base is a layer of heavily doped p-type single-crystal SiGeC, and the emitter is a layer of n-type single-crystal Si. At the heterointerface between the layer of n-type single-crystal SiGe and the layer of p-type single-crystal SiGeC, the bandgap of the p-type single-crystal SiGeC is larger than that of the layer of n-type single-crystal SiGe. Even though the effective neutral base expands due to an increase in electrons injected from the emitter, no energy barrier occurs in the conduction band at the heterointerface between the layer of n-type single-crystal SiGe and the layer of p-type single-crystal SiGeC.
    Type: Grant
    Filed: November 20, 2002
    Date of Patent: December 23, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Isao Suzumura, Katsuya Oda, Katsuyoshi Washio
  • Patent number: 6653715
    Abstract: A bipolar transistor using a B-doped Si and Ge alloy for a base in which a Ge content in an emitter-base depletion region and in a base-collector depletion region is greater than a Ge content in a base layer. Diffusion of B from the base layer can be suppressed by making the Ge content in the emitter-base depletion region and in a base-collector depletion region on both sides of the base layer greater than the Ge content in the base layer since the diffusion coefficient of B in the SiGe layer is lowered as the Ge contents increases.
    Type: Grant
    Filed: September 10, 2002
    Date of Patent: November 25, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Masao Kondo, Katsuya Oda, Katsuyoshi Washio
  • Publication number: 20030205722
    Abstract: A bipolar transistor is provided which is of high reliability and high gain, and which is particularly suitable to high speed operation. The bipolar transistor operates with high accuracy and with no substantial change of collector current even upon change of collector voltage. It also has less variation than conventional bipolar transistors for the collector current while ensuring high speed properties and high gain. In one example, the band gap in the base region is smaller than the band gap in the emitter and collector regions. The band gap is constant near the junction with the emitter region and decreases toward the junction with the collector region. A single crystal silicon/germanium is a typically used for the base region.
    Type: Application
    Filed: June 10, 2003
    Publication date: November 6, 2003
    Inventors: Katsuyoshi Washio, Reiko Hayami, Hiromi Shimamoto, Masao Kondo, Katsuya Oda, Eiji Oue, Masamichi Tanabe
  • Patent number: 6600178
    Abstract: A bipolar transistor is provided which is of high reliability and high gain, and which is particularly suitable to high speed operation. The bipolar transistor operates with high accuracy and with no substantial change of collector current even upon change of collector voltage. It also has less variation than conventional bipolar transistors for the collector current while ensuring high speed properties and high gain. In one example, the band gap in the base region is smaller than the band gap in the emitter and collector regions. The band gap is constant near the junction with the emitter region and decreases toward the junction with the collector region. A single crystal silicon/germanium is a typically used for the base region.
    Type: Grant
    Filed: June 23, 2000
    Date of Patent: July 29, 2003
    Assignees: Hitachi, Ltd., Hitachi DeviceEngineering Co., Ltd.
    Inventors: Katsuyoshi Washio, Reiko Hayami, Hiromi Shimamoto, Masao Kondo, Katsuya Oda, Eiji Oue, Masamichi Tanabe
  • Publication number: 20030103772
    Abstract: In an optical transmitter comprising a laser module including a laser diode and a monitor photodiode, a laser drive circuit for supplying a drive current to the laser module and an APC circuit for applying a bias current to the laser module on the basis of a detection signal from the monitor photodiode so that the output level of the laser module becomes constant, there is further provided an extinction ratio control circuit including an RF signal generating circuit, a low-pass filter and a peak detecting circuit. The extinction ratio control circuit superimposes an RF signal on an input data signal to the laser drive circuit to control the amplification degree of the laser drive circuit on the basis of the RF signal of the detection signal from the monitor photodiode so that the extinction ratio of the output light from the laser module becomes constant.
    Type: Application
    Filed: November 8, 2002
    Publication date: June 5, 2003
    Inventors: Yoshikazu Ishii, Katsuya Oda, Masato Tanaka, Hiroaki Asano
  • Publication number: 20030098465
    Abstract: A high-speed heterojunction bipolar transistor in a large injection of electrons from the emitter and a method for production thereof. In a typical example of the SiGeC heterojunction bipolar transistor, the collector has a layer of n-type single-crystal Si and a layer of n-type single-crystal SiGe, the base is a layer of heavily doped p-type single crystal SiGeC, and the emitter is a layer of n-type single-crystal Si. At the heterointerface between the layer of n-type single-crystal SiGe and the layer of p-type single-crystal SiGeC, the bandgap of the p-type single-crystal SiGeC is larger than that of the layer of n-type single crystal SiGe. Even though the effective neutral base expands due to an increase in electrons injected from the emitter, no energy barrier occurs in the conduction band at the heterointerface between the layer of n-type single-crystal SiGe and the layer of p-type single-crystal SiGeC.
    Type: Application
    Filed: November 20, 2002
    Publication date: May 29, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Isao Suzumura, Katsuya Oda, Katsuyoshi Washio