Patents by Inventor Katsuya Okumura

Katsuya Okumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070126041
    Abstract: A dielectric film capacitor includes a lower electrode having an opening and formed of a material including platinum, a dielectric film provided over the lower electrode and including an oxide having an ABOx crystal structure, and an upper electrode provided over the dielectric film. The planar area of the lower electrode is 50% or more of the area of a formation region of the dielectric film. A dielectric film capacitor includes a lower electrode formed of a material including platinum and having a thickness of 10 to 100 nm, a dielectric film provided over the lower electrode and including an oxide having an ABOx crystal structure, and an upper electrode provided over the dielectric film.
    Type: Application
    Filed: August 23, 2006
    Publication date: June 7, 2007
    Applicants: TOKYO ELECTRON LIMITED, Ibiden Company Limited, OCTEC Incorporated
    Inventors: Tomotaka Shinoda, Kinji Yamada, Takahiro Kitano, Yoshiki Yamanishi, Muneo Harada, Tatsuzo Kawaguchi, Yoshihiro Hirota, Katsuya Okumura, Shuichi Kawano
  • Publication number: 20070122291
    Abstract: [Problem] To always perform accurate pressure feedback control, and control the discharge flow rate of liquid chemical with high precision, even in situations in which the pressure setting value of the operation pressure differs due to changes in the type of liquid chemical, etc. [Means of solution] A pump 11 has a pump chamber 13 and an operation chamber 14 separated by a diaphragm 12 comprised of a flexible membrane, and performs the intake and discharge of liquid chemical in accordance with the change in pressure inside the operation chamber 14. An electro-pneumatic regulator 32 supplies operation air to the operation chamber 14. In addition, in the present system, a plurality of pressure sensors 51, 63 having different pressure detection ranges is provided as pressure detection means for detecting the operation air pressure.
    Type: Application
    Filed: October 17, 2006
    Publication date: May 31, 2007
    Applicants: OCTEC INC., CKD CORPORATION
    Inventors: Katsuya Okumura, Tetsuya Toyoda, Tomohiro Ito, Akira Murakumo, Atsuyuki Sakai
  • Patent number: 7195846
    Abstract: A photomask blank having a film of at least one layer formed on a substrate is manufactured by forming a film on a substrate and irradiating the film with light from a flash lamp. A photomask is manufactured from the thus manufactured photomask blank by forming a patterned resist on the film on the blank by photolithography, etching away those portions of the film which are not covered with the resist, and removing the resist. The photomask blank and photomask have minimized warpage and improved chemical resistance.
    Type: Grant
    Filed: December 2, 2003
    Date of Patent: March 27, 2007
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Hideo Kaneko, Yukio Inazuki, Tetsushi Tsukamoto, Masayuki Mogi, Katsuya Okumura
  • Patent number: 7193221
    Abstract: The present invention provides an electron optical lens column suitable for miniaturization, and provides the manufacturing method thereof. The column unit (1) comprises an inner column (11) and an outer column (12). The column unit is, as a whole, structured from a high-resistance electrically conductive ceramic. Electrostatic lenses (21, 22, 23, and 24) are affixed to the inner surface (111) of the inner column using a means such as plating or vapor deposition. Of the electrodes or electrode parts (211–213, 221, 231, 232, and 241–243) from which the lens is structured, those that share the same electric potential are connected by shared interconnections. This makes it possible to connect all of the electrodes or electrode parts with shared electric potentials as a group to the external interconnections.
    Type: Grant
    Filed: June 10, 2003
    Date of Patent: March 20, 2007
    Assignee: Toudai TLO, Ltd.
    Inventors: Katsuya Okumura, Motosuke Miyoshi
  • Publication number: 20060255182
    Abstract: Using a silicon single crystal with (100) plane orientation as a base material, a pectinate portion having a slope portion and a patterning material guiding groove is formed through photolithography process. A liquid reservoir for keeping a patterning material common to tooth portions of the pectinate portion is formed in the same step as a step for forming the guiding grooves. In forming slope portion, anisotropic wet etching allows easy and accurate formation of a slope portion with (111) plane orientation to (100) plane orientation, by taking advantage of differences in speed due to the plane orientations. In addition, by forming a groove portion using anisotropic dry etching, the patterning material guiding groove having a perpendicular sidewall reaching the slope portion may be formed at high accuracy. A pattern forming apparatus with high accuracy and low cost is provided.
    Type: Application
    Filed: April 27, 2006
    Publication date: November 16, 2006
    Inventors: Katsuya Okumura, Manabu Yabe, Yasuyuki Koyagi, Muneo Harada, Tomofumi Kiyomoto
  • Publication number: 20060252044
    Abstract: There are provided a biochip and a biochip kit, in which a target contained in an analyte is reacted with a probe with high efficiency in a short time, B/F separation efficiency is high, and high-sensitive quantitative determination and detection can be realized, and a production process thereof, and a method for reacting a target contained in an analyte with a probe, and, for example, separation and fractionation method and a detection and identification method for a target contained in an analyte, using the biochip kit. The biochip according to the present invention comprises a well(s) provided with a filter comprising straight pores, with a uniform pore diameter, provided at uniform pore spacings. A dispersion with probe-supported particles dispersed therein is contained in the well, and an analyte is placed in the well(s) to react the analyte with the probe-supported particles. A solution such as an analyte solution can be introduced into or discharged from the well through the filter.
    Type: Application
    Filed: April 23, 2004
    Publication date: November 9, 2006
    Applicant: JSR Corporation
    Inventors: Katsuya Okumura, Makoto Mihara, Mutsuhiko Yoshioka
  • Publication number: 20060247343
    Abstract: A flame-retardant synthetic resin composition characterized by comprising 1-40 parts by weight of at least one type of organic phosphorus compound represented by the following general formula (1): (wherein R1 represents alkyl, aralkyl, etc.) with respect to 100 parts by weight of a synthetic resin.
    Type: Application
    Filed: March 24, 2004
    Publication date: November 2, 2006
    Applicants: Sanko Co., Ltd., Nicca Chemical Co., Ltd.
    Inventors: Daishiro Kishimoto, Toru Makino, Katsuya Okumura, Juji Uchida
  • Patent number: 7108589
    Abstract: A polishing apparatus and method has a function of polishing a surface of a film formed on a substrate to a flat mirror finish and a function of polishing unnecessary metal film such as copper film deposited on an outer peripheral portion of the substrate to remove such unnecessary metal film. The polishing apparatus comprises a surface polishing mechanism comprising a polishing table having a polishing surface and a top ring for holding the substrate and pressing the substrate against the polishing surface of the polishing table to thereby polish a surface of the substrate, and an outer periphery polishing mechanism for polishing an outer peripheral portion of the substrate.
    Type: Grant
    Filed: July 25, 2005
    Date of Patent: September 19, 2006
    Assignees: Ebara Corporation, Kabushiki Kaisha Toshiba
    Inventors: Norio Kimura, Mitsuhiko Shirakashi, Katsuya Okumura, You Ishii, Junji Kunisawa, Hiroyuki Yano
  • Publication number: 20060192253
    Abstract: A semiconductor device that improves the heat cycle resistance and power cycle resistance of a power module. An electrode member in which copper posts are formed in a plurality of perforations cut in a support made of a ceramic material is soldered onto a side of an IGBT where an emitter electrode is formed. By soldering the copper posts onto the electrode, heat generated in the IGBT is transferred to the electrode member and is radiated. In addition, even if a material of which the IGBT is made and copper differ in thermal expansivity, stress on a soldered interface is reduced and distortion is reduced. This suppresses the appearance of a crack. As a result, the heat cycle resistance and power cycle resistance of a power module can be improved.
    Type: Application
    Filed: February 10, 2006
    Publication date: August 31, 2006
    Applicants: Octec, Inc., Fuji Electric Device Technology Co., Ltd., Kyocera Corporation
    Inventors: Katsuya Okumura, Yoshikazu Takahashi, Kazunori Takenouchi
  • Publication number: 20060172665
    Abstract: A polishing tool is used for polishing a workpiece (13) such as a semiconductor wafer to a flat mirror finish. The polishing tool has a polishing table (10) and a polishing pad (11) attached to an upper surface of the polishing table (10). The polishing pad (11) has a plurality of polishing pad pieces (111) attached to the polishing table (10). It is possible to facilitate adjustment of polishing performance over a surface of the workpiece (13) and replacement of a polishing pad (10).
    Type: Application
    Filed: March 12, 2004
    Publication date: August 3, 2006
    Inventors: Katsuya Okumura, Manabu Tsujimura
  • Patent number: 7084005
    Abstract: The present invention relates to a semiconductor device in which an electrode of a device formed on a substrate such as a semiconductor wafer and an electrode of a wiring structure such as an interposer are connected to each other through a connecting electrode extending through the substrate, and a method of manufacturing the same. A semiconductor device according to the present invention includes a first substrate including a front surface and a back surface, a first device having a first electrode being formed on the front surface; and a wiring structure formed with a second electrode, the wiring structure having a principal surface. The first electrode of the first device and the second electrode of the wiring structure are connected to each other by a connecting electrode extending through the first substrate from the front surface to the back surface thereof. Substantially all the back surface of the first substrate is bonded to the principal surface of the wiring structure.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: August 1, 2006
    Assignees: Octec Inc., Tokyo Electron Limited, Sharp Kabushiki Kaisha, Ibiden Co., Ltd.
    Inventors: Katsuya Okumura, Koji Maruyama, Kazuya Nagaseki, Akiteru Rai
  • Patent number: 7079994
    Abstract: A user is requested to input specifications of a semiconductor device. Based on the specifications, a plurality of circuit patterns are generated by a CP method, and a design parameter is calculated for each of the circuit patterns. The user is provided with information of the plurality of circuit patterns together with the design parameters. The user selects a desired circuit pattern, whereas the server calculates manufacturing costs of the device and presents them to the user. The user checks the costs and then places an order.
    Type: Grant
    Filed: July 26, 2001
    Date of Patent: July 18, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryoichi Inanami, Shunko Magoshi, Katsuya Okumura
  • Publication number: 20060154473
    Abstract: The present invention relates to a semiconductor device in which an electrode of a device formed on a substrate such as a semiconductor wafer and an electrode of a wiring structure such as an interposer are connected to each other through a connecting electrode extending through the substrate, and a method of manufacturing the same. A semiconductor device according to the present invention comprises a first substrate including a front surface and a back surface, a first device having a first electrode being formed on the front surface; and a wiring structure formed with a second electrode, the wiring structure having a principal surface. The first electrode of the first device and the second electrode of the wiring structure are connected to each other by a connecting electrode extending through the first substrate from the front surface to the back surface thereof. Substantially all the back surface of the first substrate is bonded to the principal surface of the wiring structure.
    Type: Application
    Filed: March 13, 2006
    Publication date: July 13, 2006
    Inventors: Katsuya Okumura, Koji Maruyama, Kazuyu Nagaseki, Akiteru Rai
  • Publication number: 20060131696
    Abstract: A semiconductor wafer has a bevel contour formed along the periphery thereof, products formed on the wafer, and an ID mark formed on the bevel contour. The ID mark shows at least the properties, manufacturing conditions, and test results of the products.
    Type: Application
    Filed: February 9, 2006
    Publication date: June 22, 2006
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tsunetoshi Arikado, Masao Iwase, Soichi Nadahara, Yuso Udo, Yukihiro Ushiku, Shinichi Nitta, Moriya Miyashita, Junji Sugamoto, Hiroaki Yamada, Hajime Nagano, Katsujiro Tanzawa, Hiroshi Matsushita, Norihiko Tsuchiya, Katsuya Okumura
  • Patent number: 7057259
    Abstract: A semiconductor wafer has a bevel contour formed along the periphery thereof, products formed on the wafer, and an ID mark formed on the bevel contour. The ID mark shows at least the properties, manufacturing conditions, and test results of the products.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: June 6, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsunetoshi Arikado, Masao Iwase, Soichi Nadahara, Yuso Udo, Yukihiro Ushiku, Shinichi Nitta, Moriya Miyashita, Junji Sugamoto, Hiroaki Yamada, Hajime Nagano, Katsujiro Tanzawa, Hiroshi Matsushita, Norihiko Tsuchiya, Katsuya Okumura
  • Patent number: 7042790
    Abstract: A semiconductor device includes a plurality of cell arrays, a selection control circuit to generate and to output a selection control signal. An array selection circuit generates internal address signals on the basis of an external address signal and the selection control signal. The array selection circuit outputs the internal address signals to the plurality of cell arrays to select ones of the cell arrays. A sales method for selling semiconductor devices includes presenting function-related information and price-related information on partially good semiconductor devices to client terminals and prompting the client terminals to provide purchase/non-purchase information and determining the possibility of successful transactions on the basis of the purchase/non-purchase information. A sales system for selling semiconductor devices uses the sales method and a sales program product for causing a computer system to sell semiconductor devices using the sales method.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: May 9, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsunetoshi Arikado, Katsuya Okumura, Kazuhide Yoneya, Masaru Koyanagi
  • Publication number: 20060084273
    Abstract: A gate insulation film is formed on a semiconductor substrate, gate electrodes are formed on the gate insulation film, and source/drain diffusion layers are formed. A silicon nitride films is formed on a side wall of the gate electrodes, a silicon oxide film is formed on the overall surface, and the silicon oxide film is etched back to have the same height as that of the gate electrodes so that the surface is flattened, and then the surface of the gate electrodes are etched by a predetermined thickness to form a first stepped portion from the silicon oxide film, the first stepped portion is filled up by a tungsten film, the surface of the tungsten film is etched by a predetermined thick ness so that a second stepped portion is formed, and then the second stepped portion is filled by a silicon nitride films.
    Type: Application
    Filed: November 10, 2005
    Publication date: April 20, 2006
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yusuke Kohyama, Nobuo Hayasaka, Katsuya Okumura
  • Patent number: 7023226
    Abstract: A zero-point detecting method of this invention is performed prior to testing the electrical characteristics of a wafer by bringing an object to be tested on a stage and probes of a probe card into contact with each other. The surface of a zero-point detection plate is made of a conductive material (e.g., copper). The zero-point detection plate is used to detect a zero point as a position where the surface of the object to be tested comes into contact with the probe pins.
    Type: Grant
    Filed: October 20, 2004
    Date of Patent: April 4, 2006
    Assignees: Octec Inc., Tokyo Electron Limited
    Inventors: Katsuya Okumura, Kunihiro Furuya
  • Patent number: 7018932
    Abstract: A method for manufacturing a semiconductor device including, forming a photosensitive-film on a substrate, carrying the substrate on which the photosensitive-film is formed, to an exposure device provided with a mask in which an on-mask-inspection-mark and an on-mask-device-pattern are formed, selectively exposing the photosensitive-film to light to transfer the on-mask-inspection-mark to the photosensitive-film to form a latent-image of the inspection-mark on the photosensitive-film, heating at least that area of the photosensitive-film in which the latent-image of the inspection-mark is formed, measuring the inspection-mark, changing set-values for the exposure device used for the selective exposure, on the basis of result of the measurement so that exposure conditions conform to the set-values, exposing the photosensitive-film on the basis of the changed set-values to transfer the on-mask-device-pattern to the photosensitive-film to form a latent image of the device-pattern on the photosensitive-film, heat
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: March 28, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinichi Ito, Tatsuhiko Higashiki, Katsuya Okumura, Kenji Kawano, Soichi Inoue
  • Patent number: 6991878
    Abstract: A photomask repair method including scanning an electron beam across a main surface of the photomask, thereby producing a pattern image of the photomask, identifying the position of a defective portion from the pattern image thus produced, and applying an electron beam to a region to be etched including a defective portion under an atmosphere of a gas capable of performing a chemical etching of a film material forming the photomask pattern, thereby removing a defect. In this method, the electron beam to be applied to the region to be etched is a shaped beam. The electron beam is set such that the side of the electron beam is applied in parallel to a borderline between a non-defective pattern and the defect.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: January 31, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shingo Kanamitsu, Takashi Hirano, Fumiaki Shigemitsu, Motosuke Miyoshi, Kazuyoshi Sugihara, Yuichiro Yamazaki, Makoto Sekine, Takayuki Sakai, Ichiro Mori, Katsuya Okumura