Abstract: A storage system 10 enables control by more processors 201 in accordance with reducing the resource size required per EP in a communication network to which MR-IOV is applied. The storage system 10 includes a plurality of processors 201 and a plurality of CMs 209. The internal network of the storage system 10 is configured such that each processor 201 is able to dual-write write data to a CM 209 in a FE-CM data transfer, and to transfer the write data from one of the dual-write CMs 209 to the BE in a CM-BE data transfer.

Abstract: A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory controller for leveling erase counts of blocks belonging to the flash memory chip. The storage controller combines the plural flash memory modules into a first logical group, translates a first address used for accessing the flash memory modules belonging to the first logical group to a second address used for handling the first address in the storage controller, and combines the plural first logical groups into a second logical group.

Abstract: The time required for starting up drives in a storage device mounted with both hard disk drives and solid state drives is shortened. A storage controller of the storage device identifies the type (HDD/SSD) of the mounted drives before starting up the drives. The storage controller thereafter performs staggered spinup to the HDDs in several batches. After the startup of HDDs is complete, the storage controller collectively starts up the SSDs. The storage controller determines the drive startup processing based on a pre-set drive startup policy such as reduction of the peak current reduction or shortening of the startup time, and the drive type identification result.

Abstract: A debug support device for debugging a multiprocessor configured by a plurality of unit processors a unit processor stop section realized by a plurality of the unit processors executing a program for each of the threads, and any one of the plurality of unit processors performing a process of stopping a unit processor executing a thread in which exception handling occurs together with unit processors executing other threads when the exception handling of software occurs by a break point of a part of the plurality of threads; and a debugging execution section for performing a debugging process of detecting information about a state of the plurality of unit processors stopped by the unit processor stop section.

Abstract: A multi-processor system with a plurality of unit processors includes: a request accepting section for accepting a first request and a second request, wherein the first request is a request to execute a program that can be executed in any of said unit processors and the second request is a request to execute a program that can be executed only in a specified unit processor among said unit processors; and a unit processor allocating section for allocating the first request and the second request accepted by said request accepting section to said unit processors according to priority of the first request and the second request.

Abstract: A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory controller for leveling erase counts of blocks belonging to the flash memory chip. The storage controller combines the plural flash memory modules into a first logical group, translates a first address used for accessing the flash memory modules belonging to the first logical group to a second address used for handling the first address in the storage controller, and combines the plural first logical groups into a second logical group.

Abstract: A purpose of the invention is to immediately return the operation in a flash memory module from low power consumption mode to regular mode. A flash memory controller having memory that stores an address translation table for translating between a logical page address and a physical page address in the flash memory chip controls regular mode and low power consumption mode of operating at lower power consumption than in regular mode by halting operation, or decreasing power supply voltage or lowering operating frequency. A flash memory module having the flash memory controller verifies data in the address translation table while low power consumption mode is set.

Abstract: A storage system includes a plurality of disk drives, and a disk controller for controlling the plurality of disk drives. The plurality of disk drives are configured from a plurality of virtual devices, to which logical devices are allocated. The disk controller apparatus comprises a channel adapter connected to the host computer, a disk adapter for accessing predetermined storage regions of the logical devices, cache memory arranged between the channel adapter and the disk adapter, a compression unit for carrying out compression processing on the data, and a power controller for controlling supplying of power to the plurality of disk drives. The disk controller forms logical devices after compression based on data compressed by the compression processing, and the logical devices after compression are allocated to the virtual devices.

Abstract: An purpose of the invention is to immediately return the operation in a flash memory module from low power consumption mode to regular mode. A flash memory controller having memory that stores an address translation table for translating between a logical page address and a physical page address in the flash memory chip controls regular mode and low power consumption mode of operating at lower power consumption than in regular mode by halting operation, or decreasing power supply voltage or lowering operating frequency. A flash memory module having the flash memory controller verifies data in the address translation table while low power consumption mode is set.

Abstract: This storage device performs deduplication of eliminating duplicated data by storing a logical address of one or more corresponding logical unit memory areas in a prescribed management information storage area of a physical unit memory area defined in the storage area provided by the flash memory chip, and executes a reclamation process of managing a use degree as the total number of the logical addresses used stored in the management information storage area and a duplication degree as the number of valid logical addresses corresponding to the physical unit memory area for each of the physical unit memory areas, and returning the physical unit memory area to an unused status when the difference of the use degree and the duplication degree exceeds a default value in the physical unit memory area.

Abstract: A multi-processor system with a plurality of unit processors includes: a semaphore setting section for setting semaphores representing preferential right to the competing of resources to be able to be identified to correspond to each of a plurality of the resources; a semaphore request determining section for determining, whether when a first unit processor among said unit processors requests to obtain a semaphore that is set to said semaphore setting section, the request is for requesting a semaphore being obtained by the second unit processor; and an exclusive controlling section for making the request by the first unit processor wait when it is determined that said request is for requesting a semaphore being obtained, and permitting to obtain the requested semaphore when it is determined that said request is for requesting a semaphore other than the semaphore being obtained by the semaphore request determining section.

Abstract: A processor includes: a plurality of processors; a process and status managing section which manages management information including information on statuses of the plurality of processors and priorities of processes being executed by the plurality of processors; a processing processor selecting section which selects one of the processors which is executing the process with a lowest priority on the basis of the management information managed by the process and status managing section; and an interrupt controlling section which transmits a requested interrupt process to the selected processor as an interrupt process request, wherein the processing processor selecting section selects the one of the processors, which is executing the process with the lowest priority, irrespective of whether each of the requested interrupt process and the processes being executed by the processors is a task process which is handled according to a predetermined schedule or an interrupt process which is handled independently of the

Abstract: This storage device performs deduplication of eliminating duplicated data by storing a logical address of one or more corresponding logical unit memory areas in a prescribed management information storage area of a physical unit memory area defined in the storage area provided by the flash memory chip, and executes a reclamation process of managing a use degree as the total number of the logical addresses used stored in the management information storage area and a duplication degree as the number of valid logical addresses corresponding to the physical unit memory area for each of the physical unit memory areas, and returning the physical unit memory area to an unused status when the difference of the use degree and the duplication degree exceeds a default value in the physical unit memory area.

Abstract: A multi-processor system includes a plurality of unit processors that operate in parallel. The system includes a suspension prohibition section for, in response to a request from at least one of the unit processors, prohibiting suspension of processing only in the requesting unit processors for which prohibiting suspension has been requested. The suspension prohibition section limits the number of unit processors for which the suspension is prohibited at the same time to a certain limited number or below.

Abstract: A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory controller for leveling erase counts of blocks belonging to the flash memory chip. The storage controller combines the plural flash memory modules into a first logical group, translates a first address used for accessing the flash memory modules belonging to the first logical group to a second address used for handling the first address in the storage controller, and combines the plural first logical groups into a second logical group.

Abstract: A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory controller for leveling erase counts of blocks belonging to the flash memory chip. The storage controller combines the plural flash memory modules into a first logical group, translates a first address used for accessing the flash memory modules belonging to the first logical group to a second address used for handling the first address in the storage controller, and combines the plural first logical groups into a second logical group.

Abstract: A storage device in which the MR-IOV is applied to an internal network of a storage controller. Data path failover can be executed in the storage device. The internal network of the storage controller is configured to enable the access of a virtual function (VF) “VF 0:0, 1” of each endpoint device (ED0-ED2) from a root port RP0. Likewise, “VF 1:0, 1” of each endpoint device can be accessed from a root port RP1. In a first data path from the RP0 to ED0 in a normal state, “VF 0:0, 1” and “MVF 0, 0” are connected by VF mapping. When a failure occurs on the first data path, the MR-PCIM executes the VF migration, whereby in the second data path from the RP1 to ED0, “VF 1:0, 1” and “MVF 0, 0” are connected by VF mapping. As a result, failover to the second data path is realized.

Abstract: To provide a processor capable of achieving high processing efficiency by performing the exclusive control between task processing and interrupt handling properly even in a multiprocessor. An interrupt processor that includes a plurality of unit processors, in which at least of the plurality of unit processors is capable of performing interrupt handling requested from the outside is configured such that the unit processor P1 of the unit processors P0 to P3 comprises an purge inhibit flag 106 for causing the unit processor P1 to enter a lock state where the purge of the task is being inhibited, a hardware semaphore unit 13 for inhibiting other unit processors from accessing a predetermined region in memory accessed by the unit processor P1 after the unit processor P1 is brought into the lock state, and an interrupt control unit 11 for inhibiting the interrupt processor from performing the interrupt handling during the execution of exclusive control.

Abstract: When the portable reproduction device 4 and the reproduction device 6 establish the communication by the near-distance communication part 56 and 72, a right state transmission means 48 of the portable reproduction 4 transmits to the reproduction device 6 the right state data based on the right data recorded at the right record part 50. Reproduction instruction acquisition means 66 of the reproduction device 6 receives the instruction to reproduce the contents for the reproduction device from the user. According to the right state data transmitted from the portable reproduction means 68 determines whether the reproduction device 6 has the right for the contents instructed to reproduced or not. When it is determined that the right exists, reproduction means 70 reproduce the contents for the reproduction device recording at the content record part 64. When it is determined that no right exists, reproduction is not permitted.

Abstract: The time required for starting up drives in a storage device mounted with both hard disk drives and solid state drives is shortened. A storage controller of the storage device identifies the type (HDD/SSD) of the mounted drives before starting up the drives. The storage controller thereafter performs staggered spinup to the HDDs in several batches. After the startup of HDDs is complete, the storage controller collectively starts up the SSDs. The storage controller determines the drive startup processing based on a pre-set drive startup policy such as reduction of the peak current reduction or shortening of the startup time, and the drive type identification result.