Abstract: Provided is a storage system including: a nonvolatile memory which stores and erases data for respective blocks; and a controller for inputting and outputting the data to and from the nonvolatile memory, wherein: the storage system has a storage area including: a rewritable area where a stored data can be erased; and a write-once area where the stored data cannot be erased; and the controller determines a block belonging to the rewritable area based on an attribute of the block, and performs a wear leveling process and a reclamation process only on the block determined as belonging to the rewritable area.

Abstract: High availability is provided in a storage system that offers expandability more inexpensively. Provided is a storage system including multiple expanders to be connected to multiple storage mediums, multiple cascades connected respectively to a prescribed number of expanders among the multiple expanders, and multiple control units for respectively controlling the multiple cascades. One end of the multiple cascades is connected with an inter-cascade link, and the inter-cascade link has a logically connected state and a logically disconnected state.

Abstract: To detect an address error in flash memory using a different data management unit from that in a hard disk drive. In cache memory, data read/written from/to a flash memory chip is managed in units of first data lengths. A page, which is the data management unit in a flash memory chip, includes a data section of a second data length from/to which a storage controller can read/write data; and a redundant section. When writing data, the storage controller creates a protection code enabling identification of a write destination page address, divides the data in the cache memory, which is managed in units of first data lengths, into pieces so that the size of each set composed of a piece of the divided write data and its protection code will be of a second data length, and writes the respective sets in a flash memory chip in units of second data lengths.

Abstract: This storage device performs deduplication of eliminating duplicated data by storing a logical address of one or more corresponding logical unit memory areas in a prescribed management information storage area of a physical unit memory area defined in the storage area provided by the flash memory chip, and executes a reclamation process of managing a use degree as the total number of the logical addresses used stored in the management information storage area and a duplication degree as the number of valid logical addresses corresponding to the physical unit memory area for each of the physical unit memory areas, and returning the physical unit memory area to an unused status when the difference of the use degree and the duplication degree exceeds a default value in the physical unit memory area.

Abstract: To provide a processor capable of achieving high processing efficiency by performing the exclusive control between task processing and interrupt handling properly even in a multiprocessor. An interrupt processor that includes a plurality of unit processors, in which at least of the plurality of unit processors is capable of performing interrupt handling requested from the outside is configured such that the unit processor P1 of the unit processors P0 to P3 comprises an purge inhibit flag 106 for causing the unit processor P1 to enter a lock state where the purge of the task is being inhibited, a hardware semaphore unit 13 for inhibiting other unit processors from accessing a predetermined region in memory accessed by the unit processor P1 after the unit processor P1 is brought into the lock state, and an interrupt control unit 11 for inhibiting the interrupt processor from performing the interrupt handling during the execution of exclusive control.

Abstract: A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory controller for leveling erase counts of blocks belonging to the flash memory chip. The storage controller combines the plural flash memory modules into a first logical group, translates a first address used for accessing the flash memory modules belonging to the first logical group to a second address used for handling the first address in the storage controller, and combines the plural first logical groups into a second logical group.

Abstract: A core yarn manufacturing apparatus includes a draft device that drafts sheath fibers of a core yarn and a core fiber supply device that supplies core fibers of the core yarn, wherein a feed-out path of the core fibers in the core fiber supply device is inclined above the draft device in such a manner that a front of the feed-out path is lower than a rear of the feed-out path with respect to a front surface of a machine frame, and wherein a CSY wind-out device and a CFY yarn guide are provided in a rear upper part of a base frame of the core fiber supply device, the wind-out device supporting a CSY package and winding out an elastic yarn, the yarn guide guiding a filament yarn drawn out from a CFY package located behind the core fiber supply device.

Abstract: In a disk array system composed of a disk controller connected to a host system and a maintenance terminal and a disk array connected to the disk controller via a disk channel, when failure occurs in a drive in the disk array, the disk controller writes data stored in a plurality of disk drives on a faulty board on which a faulty drive is mounted into substitution disk drives and informs the maintenance terminal that the faulty board is replaceable after the reorganization of logical groups is completed.

Abstract: A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory controller for leveling erase counts of blocks belonging to the flash memory chip. The storage controller combines the plural flash memory modules into a first logical group, translates a first address used for accessing the flash memory modules belonging to the first logical group to a second address used for handling the first address in the storage controller, and combines the plural first logical groups into a second logical group.

Abstract: A storage system includes a plurality of disk drives, and a disk controller for controlling the plurality of disk drives. The plurality of disk drives are configured from a plurality of virtual devices, to which logical devices are allocated. The disk controller apparatus comprises a channel adapter connected to the host computer, a disk adapter for accessing predetermined storage regions of the logical devices, cache memory arranged between the channel adapter and the disk adapter, a compression unit for carrying out compression processing on the data, and a power controller for controlling supplying of power to the plurality of disk drives. The disk controller forms logical devices after compression based on data compressed by the compression processing, and the logical devices after compression are allocated to the virtual devices.

Abstract: An purpose of the invention is to immediately return the operation in a flash memory module from low power consumption mode to regular mode. A flash memory controller having memory that stores an address translation table for translating between a logical page address and a physical page address in the flash memory chip controls regular mode and low power consumption mode of operating at lower power consumption than in regular mode by halting operation, or decreasing power supply voltage or lowering operating frequency. A flash memory module having the flash memory controller verifies data in the address translation table while low power consumption mode is set.

Abstract: A processor includes: a plurality of processors; a process and status managing section which manages management information including information on statuses of the plurality of processors and priorities of processes being executed by the plurality of processors; a processing processor selecting section which selects one of the processors which is executing the process with a lowest priority on the basis of the management information managed by the process and status managing section; and an interrupt controlling section which transmits a requested interrupt process to the selected processor as an interrupt process request, wherein the processing processor selecting section selects the one of the processors, which is executing the process with the lowest priority, irrespective of whether each of the requested interrupt process and the processes being executed by the processors is a task process which is handled according to a predetermined schedule or an interrupt process which is handled independently of the

Abstract: A storage system is disclosed for performing control to match data among cache memories corresponding to shared volumes when multiple disk controllers containing cache memories are accessing shared volumes formed in the storage device. The storage system contains a switch for switching and connecting the multiple disk controllers containing cache memories, with a disk array containing the shared volumes capable of being commonly accessed from the multiple disk controllers. The switch performs exclusive access control of the multiple disk controllers' writing on the shared volumes, and performs control to match data other than modified data among the cache memories.

Abstract: When the capacity availability of buffer memory provided to an output port of a frame to be transferred is exceeding a predetermined value, a crossbar switch is used for path change of the frame. When the capacity availability of the buffer memory of the output port is the predetermined value or lower, the frame is written into shared memory. Then, the frame is read from the shared memory for transfer to the output port. By selectively performing frame transfer using the crossbar switch and frame transfer via the shared memory, the effects can be reduced even if the port buffer overflows, and the writing throughput can be favorably improved.

Abstract: A disk device has a chassis, disk drives, wiring boards for the disk drives and blowers for cooling the disk drives. The disk drives are arranged in height and depth directions in the chassis. The disk drives are spaced each other with a predetermined distance and attached to the wiring boards so that a disk surface of rotation of each disk drive is perpendicular to a board surface of a wiring board. The disk device further includes drawer units which provide simultaneous extraction of the disk drives, the wiring boards and the blowers from the chassis.

Abstract: A processor or a semiconductor integrated circuit has circuit blocks performing signal processing, internal power supply nets, noise detecting circuits corresponding to each circuit block that detect noise on the power supply nets and an interruption handling circuit that prevents a malfunction in processing within a circuit block caused by noise on the power supply nets. When noise is detected, the interruption handling circuit performs an interruption by sending an interruption signal to the circuit block relating to the signal processing for preventing a malfunction to the circuit block. During the operation of a plurality of stages for executing an instruction, noise is monitored at every stage. If no noise is detected through a final stage, the result is outputted. If noise is detected at any one of the stages, then an interruption process is performed.

Abstract: To detect an address error in flash memory using a different data management unit from that in a hard disk drive. In cache memory, data read/written from/to a flash memory chip is managed in units of first data lengths. A page, which is the data management unit in a flash memory chip, includes a data section of a second data length from/to which a storage controller can read/write data; and a redundant section. When writing data, the storage controller creates a protection code enabling identification of a write destination page address, divides the data in the cache memory, which is managed in units of first data lengths, into pieces so that the size of each set composed of a piece of the divided write data and its protection code will be of a second data length, and writes the respective sets in a flash memory chip in units of second data lengths.

Abstract: A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory controller for leveling erase counts of blocks belonging to the flash memory chip. The storage controller combines the plural flash memory modules into a first logical group, translates a first address used for accessing the flash memory modules belonging to the first logical group to a second address used for handling the first address in the storage controller, and combines the plural first logical groups into a second logical group.

Abstract: A multi-processor system with a plurality of unit processors in which the unit processors can operate in parallel includes: a suspension prohibition section for, in response to a request from at least one of the unit processors, prohibiting suspension that suspends, only in the requesting unit processor, processing executed in the unit processor.

Abstract: A debug support device for debugging a multiprocessor configured by a plurality of unit processors includes a unit processor stop section realized by a plurality of the unit processors executing a program for each of the threads, and any one of the plurality of unit processors performing a process of stopping a unit processor executing a thread in which exception handling occurs together with unit processors executing other threads when the exception handling of software occurs by a break point of a part of the plurality of threads; and a debugging execution section for performing a debugging process of detecting information about a state of the plurality of unit processors stopped by the unit processor stop section.