Abstract: In order to stably generate a high voltage of a prescribed level, a Vpp detection circuit which is activated in response to an activation signal for comparing the high voltage with a reference voltage is forcibly brought into an active state for a prescribed period under control of an initial control circuit.

Abstract: An address generating circuit of a DRAM includes five fuses, a trimming switching circuit generating five signals in accordance with whether or not each fuse is blown, a voltage converting circuit generating a control voltage of a level corresponding to the five signals, a voltage control oscillation circuit generating a clock signal of a cycle according to the control voltage, and an address counter generating an address signal in synchronization with the clock signal. Thus, unlike a conventional example, a plurality of counting circuits and a detection circuit are eliminated, resulting in reduction of power consumption and circuit scale.

Abstract: In order to stably generate a high voltage of a prescribed level, a Vpp detection circuit which is activated in response to an activation signal for comparing the high voltage with a reference voltage is forcibly brought into an active state for a prescribed period under control of an initial control circuit.

Abstract: In the present semiconductor integrated circuit device, a buffer is provided between a constant-current source circuit and an internal circuit that becomes a source of noise. The buffer controls the potential of an output node such that the potential of the output node becomes the bias potential. Even when noise is generated on the bias potential line when the internal circuit is in operation, the buffer dampens the noise. Thus, the noise generated in the internal circuit is prevented from adversely affecting the constant-current source circuit, and a stable operation of the internal circuit itself is achieved.

Abstract: A semiconductor memory device includes a voltage detection circuit. The voltage detection circuit uses a voltage division circuit to derive from a test command voltage forming a test command signal EXTSH a voltage fraction which is one-third of the original voltage and uses another voltage division circuit to derive from an external supply voltage a voltage fraction which is a half of the original voltage. The two voltage fractions are compared by a comparison circuit of differential amplification type to detect the test command voltage and cause transition of a test target circuit of the semiconductor memory device to a test mode. P channel MOS transistors constituting the voltage division circuits all operate in resistance mode. The test command signal of high-voltage can thus be detected.

Abstract: A through-current Ic of a comparator circuit is switched in accordance with a response speed required with respect to a current consumption. Additionally, a through-current Is of a shifter circuit, which sends to the comparator circuit an output signal at an appropriate level transmitting a difference between an internal power supply potential Vdd and a reference potential Vref is switched according to the required response speed. When a device is in a standby state requiring a small current consumption in internal power supply potential Vdd, both through-currents Ic and Is are set small so that the whole current consumption can be further reduced.

Abstract: An internal power supply circuit produces an internal power supply voltage from an external power supply voltage. A voltage level control circuit controls a voltage level and a temperature characteristic of the internal power supply voltage generated by the internal power supply circuit. The internal power supply circuit produces the internal power supply voltage having a negative or zero temperature characteristic in a low temperature region and a positive temperature characteristic in a high temperature region. The voltage level control circuit includes a structure optimizing a capacitance value of a sense power supply line stabilizing capacitance for driving a sense amplifier circuit, a level converting circuit determining the lowest operable region of the external power supply voltage of the internal power supply circuit, or a structure forcedly operating the internal voltage down converter upon power-on.

Abstract: A control circuit & mode register outputs a signal responsive to each command to a VDC control circuit. The VDC control circuit outputs a signal PWRUP changing the quantity of a through current Ic of a comparator stored in a VDC in response to the command. The VDC control circuit internally generates a signal of which pulse width corresponds to a prescribed delay time, in response to input of the command. Therefore, activation of each bank may not be monitored but current consumption can be reduced by preferably controlling a power supply current while minimizing the number of delay circuits and wires.

Abstract: In order to stably generate a high voltage of a prescribed level, a Vpp detection circuit which is activated in response to an activation signal for comparing the high voltage with a reference voltage is forcibly brought into an active state for a prescribed period under control of an initial control circuit.

Abstract: A Vpp level detecting circuit detects a potential on a Vpp trunk line which is provided commonly to a plurality of memory array banks for supplying a boosted potential thereto, and a boosted potential pump circuit supplies a current to the Vpp trunk line in accordance with a result of the detection. Since the position on the Vpp trunk line where the Vpp level detecting circuit performs the monitoring is substantially equally spaced from the respective memory blocks, an influence caused by an active state of the memory array bank can be suppressed during control of the potential on the Vpp trunk line.

Abstract: In order to stably generate a high voltage of a prescribed level, a Vpp detection circuit which is activated in response to an activation signal for comparing the high voltage with a reference voltage is forcibly brought into an active state for a prescribed period under control of an initial control circuit.

Abstract: A semiconductor integrated circuit includes a node for the power supply voltage for array that is connected to a sense amplifier, a decoupling capacitance connected to the node for the power supply voltage for array, a voltage-down converter connected to the node for the power supply voltage for array and generating a largest voltage stored in a memory cell, and two voltage-down converters connected to the node for the power supply voltage for array and generating a voltage higher than the largest voltage, and boosts the voltage of the node for the power supply voltage for array to attain a voltage higher than the largest voltage in the stand-by state and activates the voltage-down converter generating the largest voltage in operation.

Abstract: A level adjusting circuit for controlling a voltage supplied to a load such as a semiconductor device, which comprises a voltage level detecting circuit, a reference potential generating circuit for generating a pair of reference potential values to be output into the voltage level detecting circuit, and a monitor pad for drawing out the voltage supplied to the load, wherein the reference potential values are respectively used to compare with the voltage to thereby output a signal for starting supply of the voltage and a signal for ceasing the supply of the voltage under a usually used condition; and the voltage level detecting circuit is to compare either one of the reference potential values with the voltage or the other reference potential value with the voltage at a time under a testing condition, whereby the reference potential generating circuit can accurately be adjusted to change the reference potential values to render the voltage in a range permissible for operation of the load.

Abstract: A semiconductor integrated circuit includes a node for the power supply voltage for array that is connected to a sense amplifier, a decoupling capacitance connected to the node for the power supply voltage for array, a voltage-down converter connected to the node for the power supply voltage for array and generating a largest voltage stored in a memory cell, and two voltage-down converters connected to the node for the power supply voltage for array and generating a voltage higher than the largest voltage, and boosts the voltage of the node for the power supply voltage for array to attain a voltage higher than the largest voltage in the stand-by state and activates the voltage-down converter generating the largest voltage in operation.

Abstract: A semiconductor integrated circuit includes a charge pump for issuing an internal power supply voltage higher than an external power supply voltage, two level detectors for detecting a magnitude of the internal power supply voltage issued from the charge pump, and a composite ring oscillator including two ring oscillators connected to these level detectors and having different oscillation frequencies, respectively. Depending on the magnitude of the internal power supply voltage issued from the charge pump, the signals generated by the ring oscillators are selectively issued to the charge pump.

Abstract: A semiconductor device allowing control of its threshold voltage without requiring change in the materials of its gate electrodes and suitable for high density integration is disclosed. The semiconductor device includes a p type monocrystalline silicon substrate 1 having a cylindrical portion with inner and outer surfaces and extending in a vertical direction. A first gate electrode 8 and a second gate electrode 10 are disposed at the inner surface and the outer surface of the cylindrical portion 2, respectively. A source/drain region 5 is formed on the top end of the cylindrical portion 2, while a source/drain region 3 is formed on the inner bottom surface of the cylindrical portion 2. Therefore, the cylindrical portion 2 can be utilized as a channel region of an MIS field effect transistor. The threshold voltage of the transistor can easily be controlled by applying separate voltages to the two gate electrodes, the first electrode and the second electrode.

Abstract: A method of and an apparatus for removing a naturally grown oxide film and contaminants on the surface of a semiconductor substrate and then forming a thin film on the cleaned surface. The semiconductor substrate is placed in a pretreatment chamber and then hydrogen chloride gas is introduced into the chamber. Then, the semiconductor substrate is heated at a temperature between 200.degree..about.700.degree. C. and the surface of the semiconductor substrate is irradiated with ultraviolet rays, whereby the naturally grown oxide film and other contaminants on the semiconductor substrate can be removed. Then, a thin film is formed on the cleaned surface of the semiconductor substrate by a CVD method or a sputter method. According to this method, the naturally oxide film and other contaminants can be removed from the surface of the semiconductor substrate at a low temperature and the thin film can be formed on the cleaned surface.

Abstract: A semiconductor device allowing control of its threshold voltage without requiring change in the materials of its gate electrodes and suitable for high density integration is disclosed. The semiconductor device includes a p type monocrystalline silicon substrate 1 having a cylindrical portion with inner and outer surfaces and extending in a vertical direction. A first gate electrode 8 and a second gate electrode 10 are disposed at the inner surface and the outer surface of the cylindrical portion 2, respectively. A source/drain region 5 is formed on the top end of the cylindrical portion 2, while a source/drain region 3 is formed on the inner bottom surface of the cylindrical portion 2. Therefore, the cylindrical portion 2 can be utilized as a channel region of an MIS field effect transistor. The threshold voltage of the transistor can easily be controlled by applying separate voltages to the two gate electrodes, the first electrode and the second electrode.

Abstract: Holes generated by impact ionization in a SOI-MOS transistor is removed from the channel region to improve the breakdown voltage between the source and drain. A channel region of the SOI-MOS transistor is formed of a p type silicon layer. A drain region is formed of an n type silicon layer. A source region adjacent to the channel region includes an n type germanium layer. The forbidden energy band gap width of the germanium is smaller than that of the silicon. The n type germanium layer is formed in at least a portion of the source region. This layer is formed by ion-implanting germanium into a portion of the silicon layer, or removing a portion of the silicon layer, followed by growing a germanium layer in an epitaxial manner thereabove.

Abstract: In a CMOS semiconductor device, a pMOS transistor and an nMOS transistor are formed on a single substrate. Each of the source/drain regions of the nMOS transistor and the pMOS transistor has LDD structure composed of a combination of a low concentration impurity region and a high concentration impurity region. The low concentration impurity region of the LDD structure of the pMOS transistor is formed in a self-align manner by ion implantation using a sidewall spacer with relatively thick film thickness. The low concentration impurity region of the LDD structure of the nMOS transistor is formed in a self-align manner by ion implantation using a relatively thin sidewall spacer as a mask. The sidewall spacer with thick film thickness of the pMOS transistor restrains that the channel between the source/drain regions is shortened due to thermal diffusion to cause punch through.