Patents by Inventor Katsuyoshi Yamamoto
Katsuyoshi Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9942120Abstract: The present invention provides a technique for measuring the efficiency of components in a computer. An echo server is provided which comprises several units. A socket generation unit generates a receiving server socket on the basis of information on a correspondence between a plurality of components in a computer. And generates a client socket that is a dedicated socket inheriting information of the receiving server socket when data is transmitted. A stream acquisition unit acquires a transmission path for acquiring data transmitted and received between components. A thread generation unit generates a transmission path by coupling streams. A transfer execution unit transfers data acquired via a thread to an original destination component. Using these units, the technique monitors and running verifies behavior by observing data running on the network.Type: GrantFiled: February 11, 2015Date of Patent: April 10, 2018Assignee: International Business Machines CorporationInventors: Kohsuke Okamoto, Katsuyoshi Yamamoto, Hiroyuki Ogura
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Patent number: 9355974Abstract: A semiconductor device includes a plurality of protrusions formed on a first face of the semiconductor device; first bonding portions formed on upper portions of the plurality of protrusions; second bonding portions formed on side faces of the plurality of protrusions; and third bonding portions formed on the first face between the plurality of protrusions, wherein the semiconductor device is configured to bond to an other semiconductor device through the third from the first bonding portions.Type: GrantFiled: August 17, 2015Date of Patent: May 31, 2016Assignee: SOCIONEXT INC.Inventors: Masashi Takenaka, Katsuyoshi Yamamoto
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Publication number: 20150357299Abstract: A semiconductor device includes a plurality of protrusions formed on a first face of the semiconductor device; first bonding portions formed on upper portions of the plurality of protrusions; second bonding portions formed on side faces of the plurality of protrusions; and third bonding portions formed on the first face between the plurality of protrusions, wherein the semiconductor device is configured to bond to an other semiconductor device through the third from the first bonding portions.Type: ApplicationFiled: August 17, 2015Publication date: December 10, 2015Inventors: Masashi Takenaka, Katsuyoshi Yamamoto
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Patent number: 9142516Abstract: A semiconductor device includes a plurality of protrusions formed on a first face of the semiconductor device; first bonding portions formed on upper portions of the plurality of protrusions; second bonding portions formed on side faces of the plurality of protrusions; and third bonding portions formed on the first face between the plurality of protrusions, wherein the semiconductor device is configured to bond to an other semiconductor device through the third from the first bonding portions.Type: GrantFiled: June 18, 2012Date of Patent: September 22, 2015Assignee: SOCIONEXT INC.Inventors: Masashi Takenaka, Katsuyoshi Yamamoto
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Publication number: 20150156099Abstract: The present invention provides a technique for measuring the efficiency of components in a computer. An echo server is provided which comprises several units. A socket generation unit generates a receiving server socket on the basis of information on a correspondence between a plurality of components in a computer. And generates a client socket that is a dedicated socket inheriting information of the receiving server socket when data is transmitted. A stream acquisition unit acquires a transmission path for acquiring data transmitted and received between components. A thread generation unit generates a transmission path by coupling streams. A transfer execution unit transfers data acquired via a thread to an original destination component. Using these units, the technique monitors and running verifies behavior by observing data running on the network.Type: ApplicationFiled: February 11, 2015Publication date: June 4, 2015Inventors: Kohsuke Okamoto, Katsuyoshi Yamamoto, Hiroyuki Ogura
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Patent number: 8966051Abstract: The present invention provides a technique for measuring the efficiency of components in a computer. An echo server is provided which comprises several units. A socket generation unit generates a receiving server socket on the basis of information on a correspondence between a plurality of components in a computer. And generates a client socket that is a dedicated socket inheriting information of the receiving server socket when data is transmitted. A stream acquisition unit acquires a transmission path for acquiring data transmitted and received between components. A thread generation unit generates a transmission path by coupling streams. A transfer execution unit transfers data acquired via a thread to an original destination component. Using these units, the technique monitors and running verifies behavior by observing data running on the network.Type: GrantFiled: January 30, 2004Date of Patent: February 24, 2015Assignee: International Business Machines CorporationInventors: Kohsuke Okamoto, Katsuyoshi Yamamoto, Hiroyuki Ogura
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Patent number: 8477384Abstract: A solid-state image pickup device and image pickup method eliminate a dark-current component by adjusting the black level appropriately even if the dark-current component varies among horizontal lines. A pixel array includes light-receiving pixel elements and light-blocking pixel elements disposed such that horizontal lines include the light-blocking pixel elements individually. A readout circuit block reads pixel signals of each of the horizontal lines from the pixel array, inputs the pixel signals to ADC circuits (column ADC circuit block), and outputs the pixel signals of the light-blocking pixel elements. A ramp signal generation circuit obtains the pixel signals of the light-blocking pixel elements output from the readout circuit block, generates a ramp signal by using a reference level of AD conversion adjusted for each of the horizontal lines in accordance with the obtained pixel signals of the light-blocking pixel elements, and inputs the ramp signal to the ADC circuits.Type: GrantFiled: September 16, 2008Date of Patent: July 2, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Toshitaka Mizuguchi, Katsuyoshi Yamamoto, Jun Funakoshi, Tsuyoshi Higuchi
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Publication number: 20130026649Abstract: A semiconductor device includes a plurality of protrusions formed on a first face of the semiconductor device; first bonding portions formed on upper portions of the plurality of protrusions; second bonding portions formed on side faces of the plurality of protrusions; and third bonding portions formed on the first face between the plurality of protrusions, wherein the semiconductor device is configured to bond to an other semiconductor device through the third from the first bonding portions.Type: ApplicationFiled: June 18, 2012Publication date: January 31, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Masashi Takenaka, Katsuyoshi Yamamoto
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Patent number: 8140552Abstract: A method for optimizing lead time for service provisioning for a request from a customer includes storing a record of installation and configuration times for each hardware and software configuration in a database, and then calculating success rates and failure rates for each hardware and software configuration. A manual installation time for the request is set in the event of failure. The necessary time to prepare the system fulfilling the customer request is then determined and displayed in the data center.Type: GrantFiled: September 19, 2008Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Masatoshi Tagami, Yoshinori Tanaka, Katsuyoshi Yamamoto
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Patent number: 8110860Abstract: First diffusion region constituting a photodiode in each pixel stores carriers generated according to incident light. Second diffusion region is formed at a surface of the first diffusion region to cover a peripheral part of the first diffusion region. In the peripheral part of the first diffusion region, crystal defects tend to occur by a process of forming an isolation region and a gate electrode, so that dark current noise tends to occur. The second diffusion region functioning as a protection layer prevents crystal defects in a manufacturing process. The second diffusion region isn't formed on a center of the surface of the first diffusion region where crystal defects don't tend to occur. In the first diffusion region where the second diffusion region isn't formed, the thickness of a depletion layer increases, which improves light detection sensitivity. This improves detection sensitivity of the photodiode without increasing the dark current noise.Type: GrantFiled: May 10, 2011Date of Patent: February 7, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Tadao Inoue, Katsuyoshi Yamamoto, Hiroshi Kobayashi
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Patent number: 8013370Abstract: A solid-state imaging device has a substrate in which are formed a pixel array portion having a plurality of pixels, and a peripheral circuitry portion. The device is characterized in that a first multilevel metallization structure is formed over the peripheral circuitry portion, and a second multilevel metallization structure thinner than the first multilevel metallization structure is formed over the pixel array portion.Type: GrantFiled: October 14, 2005Date of Patent: September 6, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Hiroshi Kobayashi, Katsuyoshi Yamamoto, Tadao Inoue, Toshitaka Mizuguchi
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Publication number: 20110210383Abstract: First diffusion region constituting a photodiode in each pixel stores carriers generated according to incident light. Second diffusion region is formed at a surface of the first diffusion region to cover a peripheral part of the first diffusion region. In the peripheral part of the first diffusion region, crystal defects tend to occur by a process of forming an isolation region and a gate electrode, so that dark current noise tends to occur. The second diffusion region functioning as a protection layer prevents crystal defects in a manufacturing process. The second diffusion region isn't formed on a center of the surface of the first diffusion region where crystal defects don't tend to occur. In the first diffusion region where the second diffusion region isn't formed, the thickness of a depletion layer increases, which improves light detection sensitivity. This improves detection sensitivity of the photodiode without increasing the dark current noise.Type: ApplicationFiled: May 10, 2011Publication date: September 1, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Tadao INOUE, Katsuyoshi YAMAMOTO, Hiroshi KOBAYASHI
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Patent number: 7964902Abstract: First diffusion region constituting a photodiode in each pixel stores carriers generated according to incident light. Second diffusion region is formed at a surface of the first diffusion region to cover a peripheral part of the first diffusion region. In the peripheral part of the first diffusion region, crystal defects tend to occur by a process of forming an isolation region and a gate electrode, so that dark current noise tends to occur. The second diffusion region functioning as a protection layer prevents crystal defects in a manufacturing process. The second diffusion region isn't formed on a center of the surface of the first diffusion region where crystal defects don't tend to occur. In the first diffusion region where the second diffusion region isn't formed, the thickness of a depletion layer increases, which improves light detection sensitivity. This improves detection sensitivity of the photodiode without increasing the dark current noise.Type: GrantFiled: September 26, 2007Date of Patent: June 21, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Tadao Inoue, Katsuyoshi Yamamoto, Hiroshi Kobayashi
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Patent number: 7882075Abstract: An automated system and method for predicting a future resource utilization tendency by analyzing a change in resource usage on the basis of a real operation condition in a computer system. A CPU utilization estimating unit acquires a resource log and a transaction log, and estimates utilization for each transaction, and information on the number of executions for each transaction, a processing amount predicting unit performs a statistical time-series analysis on the basis of time-series data of the number of executions for each transaction included in the transaction log and predicts an amount of processing for each type of a transaction, and a resource utilization predicting unit predicts the computer resource utilization or demand on from the estimated resource utilization for each transaction and the future predicted amount of processing for each transaction.Type: GrantFiled: May 16, 2008Date of Patent: February 1, 2011Assignee: International Business Machines CorporationInventors: Yasuhiro Suzuki, Katsuyoshi Yamamoto, Naoya Yamamoto
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Publication number: 20100283879Abstract: A solid-state image pickup apparatus includes a pixel unit consisting of a plurality of pixels; a pixel control unit for controlling the plurality of pixels; a readout unit for reading a signal of each pixel output from the pixel unit; a shutter unit for establishing a state of a light incident to the pixel unit and that of shielding the pixel unit from the light; and a control unit. The control unit includes an exposure mode changeover unit for changing over an exposure mode to either a first exposure mode performing a simultaneous exposure for all pixels or a second exposure mode performing an exposure for each of a predetermined unit of pixels. The control unit controls the pixel control unit, readout unit and shutter unit according to an exposure mode changed over by the exposure mode changeover unit.Type: ApplicationFiled: July 26, 2010Publication date: November 11, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Tadao Inoue, Katsuyoshi Yamamoto
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Patent number: 7777796Abstract: A solid-state image pickup apparatus includes a pixel unit consisting of a plurality of pixels; a pixel control unit for controlling the plurality of pixels; a readout unit for reading a signal of each pixel output from the pixel unit; a shutter unit for establishing a state of a light incident to the pixel unit and that of shielding the pixel unit from the light; and a control unit. The control units includes an exposure mode changeover unit for changing over an exposure mode to either a first exposure mode performing a simultaneous exposure for all pixels or a second exposure mode performing an exposure for each of a predetermined unit of pixels. The control unit controls the pixel control unit, readout unit and shutter unit according to an exposure mode changed over by the exposure mode changeover unit.Type: GrantFiled: October 11, 2006Date of Patent: August 17, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Tadao Inoue, Katsuyoshi Yamamoto
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Publication number: 20100188542Abstract: An imaging device includes a pixel array that includes a plurality of pixels, a data read circuit that sequentially reads the data of a given line from the pixel array, a plurality of column analog-digital converters that perform analog-digital conversion on the data from the data read circuit, and a control signal generating circuit that generates a control signal to control the analog-digital conversion.Type: ApplicationFiled: January 22, 2010Publication date: July 29, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Toshitaka MIZUGUCHI, Katsuyoshi Yamamoto
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Patent number: 7745860Abstract: A CMOS image sensor with an effectively increased aperture ratio and moreover with improved optical sensitivity, and a method of manufacture of such a CMOS image sensor is provided a first aspect of the invention is an image sensor, has a pixel region 10 in which are formed a plurality of pixels each having at least a photodiode, a reset transistor, and a source-follower transistor; and a peripheral circuit region 12 in which are formed peripheral circuits which process read-out signals read out from the pixel region, a well region PW2 in the pixel region PW1 is formed to be more shallow than a well region in the peripheral circuit region. Also, reset transistors or source-follower transistors are formed in the shallow well region PW2 of the pixel region 10, and a photodiode region PHD2 is embedded below the transistor well region PW2.Type: GrantFiled: September 10, 2007Date of Patent: June 29, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Tadao Inoue, Katsuyoshi Yamamoto, Narumi Ohkawa
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Publication number: 20100082528Abstract: A method for optimizing lead time for service provisioning for a request from a customer includes storing a record of installation and configuration times for each hardware and software configuration in a database, and then calculating success rates and failure rates for each hardware and software configuration. A manual installation time for the request is set in the event of failure. The necessary time to prepare the system fulfilling the customer request is then determined and displayed in the data center.Type: ApplicationFiled: September 19, 2008Publication date: April 1, 2010Inventors: Masatoshi Tagami, Yoshinori Tanaka, Katsuyoshi Yamamoto
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Patent number: 7639290Abstract: A differential amplifier has a first input terminal to which a voltage of a noise signal of the solid-state imaging device is supplied and a second input terminal to which a voltage of a temporary data signal having the noise signal of the solid-state imaging device superposed thereon is supplied. The differential amplifier inverts an output signal when a magnitude relationship in voltage between the first and second input terminals becomes reverse. A measurement circuit measures a variation amount of a voltage of the second input terminal from when the voltage of the second input terminal begins to vary in a direction to reverse the magnitude relationship to when the output signal of the differential amplifier is inverted, and outputs a measurement result as a digital value indicating a voltage of a real data signal obtained by removing the noise signal from the temporary data signal.Type: GrantFiled: May 27, 2005Date of Patent: December 29, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Tsuyoshi Higuchi, Jun Funakoshi, Seiji Yamagata, Toshitaka Mizuguchi, Katsuyoshi Yamamoto