Abstract: A reconfigured semiconductor logic device includes a semiconductor logic device comprising a plurality of input/output (I/O) pads formed on an active surface thereof and a redistribution layer. The redistribution layer comprises an insulating layer formed atop the active surface of the semiconductor logic device such that the insulating layer does not extend beyond an outer perimeter of the active surface and a patterned conductive wiring layer positioned above the insulating layer. The patterned conductive wiring layer includes a plurality of terminal buses formed on a top surface of the insulating layer. Each terminal bus of the plurality of terminal buses is electrically coupled to multiple I/O pads of the plurality of I/O pads through vias formed in the insulating layer.

Abstract: A reconfigured semiconductor device includes a semiconductor device comprising an active surface having a plurality of input/output (I/O) pads spaced at a non-solderable pitch thereon and at least one redistribution layer overlying the active surface of the semiconductor device. Each at least one redistribution layer includes an insulating layer and a patterned conductive layer comprising a plurality of discrete terminal pads formed on the insulating layer, each of the plurality of discrete terminal pads electrically coupled to a respective I/O pad of the plurality of I/O pads by a conductive via formed through the insulating layer.

Abstract: A reconfigured semiconductor logic device includes a semiconductor logic device comprising an active surface having a plurality of input/output (I/O) pads formed thereon and a redistribution layer. The redistribution layer includes an insulating layer disposed on the active surface of the semiconductor logic device and a patterned conductive layer comprising a plurality of discrete terminal pads formed atop the insulating layer. The plurality of discrete terminal pads are electrically coupled to respective I/O pads of the plurality of I/O pads by conductive vias formed through the insulating layer. The plurality of discrete terminal pads are larger than the plurality of I/O pads.

Abstract: An electronics package includes an interconnect assembly comprising a first insulating substrate, a first wiring layer formed on a lower surface of the first insulating substrate, and at least one through hole extending through the first insulating substrate and the first wiring layer. The electronics package also includes an electrical component assembly comprising an electrical component having an active surface coupled to an upper surface of the first insulating substrate opposite the lower surface. The active surface of the electrical comprises at least one metallic contact pad. At least one conductive stud is coupled to the at least one metallic contact pad and is positioned within the at least one through hole. A conductive plug contacts the first wiring layer and extends into the at least one through hole to at least partially surround the at least one conductive stud.

Abstract: A reconfigured semiconductor device includes a semiconductor device comprising an active surface having a plurality of input/output (I/O) pads spaced at a non-solderable pitch thereon and at least one redistribution layer overlying the active surface of the semiconductor device. Each at least one redistribution layer includes an insulating layer and a patterned conductive layer comprising a plurality of discrete terminal pads formed on the insulating layer, each of the plurality of discrete terminal pads electrically coupled to a respective I/O pad of the plurality of I/O pads by a conductive via formed through the insulating layer.

Abstract: An embedded semiconductor package includes a semiconductor logic device comprising a plurality of signal input/output (I/O) pads spaced at a first pitch on an active surface thereof and a plurality of power I/O pads and ground I/O pads spaced on the active surface at a second pitch larger than the first pitch. At least one interconnect layer overlies the semiconductor logic device. Each of the at least one interconnect layers includes an insulating layer and a conductive layer formed on the insulating layer and extending into a plurality of vias formed therethrough. The conductive layer is electrically coupled to the plurality of signal I/O pads and the plurality of power I/O pads and ground I/O pads.

Abstract: An electronics package includes a support substrate, an electrical component having an active surface coupled to a first surface of the support substrate, and an insulating structure coupled to the first surface of the support substrate and at least one side wall of the electrical component. A functional layer comprising at least one functional component is formed on at least one of a sloped side wall of the insulating structure and a backside surface of the electrical component. A first wiring layer is formed on a second surface of the support substrate. The first wiring layer is electrically coupled to the functional layer through at least one via in the support substrate.

Abstract: An electronics package includes an insulating substrate, an electrical component having an active surface coupled to a first surface of the insulating substrate, and an insulating structure disposed adjacent the electrical component on the first surface of the insulating substrate. A first wiring layer is formed on a top surface of the insulating structure and extends down at least one sloped side surface of the insulating structure. A second wiring layer is formed on a second surface of the insulating substrate. The second wiring layer extends through a plurality of vias in the insulating substrate to electrically couple at least one contact pad on the active surface of the electrical component to the first wiring layer.

Abstract: An electronics package includes a support substrate, an electrical component having a first surface coupled to a first surface of the support substrate, and an insulating structure coupled to the first surface of the support substrate and sidewalls of the electrical component. The insulating structure has a sloped outer surface. A conductive layer encapsulates the electrical component and the sloped outer surface of the insulating structure. A first wiring layer is formed on a second surface of the support substrate. The first wiring layer is coupled to the conductive layer through at least one via in the support substrate.

Abstract: A method of manufacturing a multi-layer electronics package includes attaching a base insulating substrate to a frame having an opening therein and such that the frame is positioned above and/or below the base insulating substrate to provide support thereto. A first conductive wiring layer is applied on the first side of the base insulating substrate, and vias are formed in the base insulating substrate. A second conductive wiring layer is formed on the second side of the base insulating substrate that covers the vias and the exposed portions of the first conductive wiring layer and at least one additional insulating substrate is bonded to the base insulating substrate. Vias are formed in each additional insulating substrate and an additional conductive wiring layer is formed on each of the additional insulating substrate. The described build-up forms a multilayer interconnect structure, with the frame providing support for this build-up.

Abstract: An electronics package includes an insulating substrate, an electrical component having a back surface coupled to a first surface of the insulating substrate, and an insulating structure surrounding at least a portion of a perimeter of the electrical component. A first wiring layer extends from the first surface of the insulating substrate and over a sloped side surface of the insulating structure to electrically couple with at least one contact pad on an active surface of the electrical component. A second wiring layer is formed on a second surface of the insulating substrate and extends through at least one via therein to electrically couple with the first wiring layer.

Abstract: An electronics package includes an interconnect assembly comprising a first insulating substrate, a first wiring layer formed on a lower surface of the first insulating substrate, and at least one through hole extending through the first insulating substrate and the first wiring layer. The electronics package also includes an electrical component assembly comprising an electrical component having an active surface coupled to an upper surface of the first insulating substrate opposite the lower surface. The active surface of the electrical comprises at least one metallic contact pad. At least one conductive stud is coupled to the at least one metallic contact pad and is positioned within the at least one through hole. A conductive plug contacts the first wiring layer and extends into the at least one through hole to at least partially surround the at least one conductive stud.

Abstract: A system includes an implantable sensor assembly. The implantable sensor assembly includes a housing. The housing includes a substrate layer comprising an interior surface and an exterior surface, and a cap layer, wherein the substrate layer and the cap layer are coupled to form an enclosed cavity that at least partially encloses the interior surface of the substrate layer within the cavity and wherein both the substrate layer and the cap layer are formed from an insulating material. The implantable sensor assembly also includes one or more electronic components disposed within the cavity of the housing and one or more probes disposed on the exterior surface of the substrate layer and electrically coupled to the one or more electronic components by one or more electrical connections extending through the housing.

Abstract: The present approach relates to the fabrication and use of a probe array having multiple individual probes. In one embodiment, the probes of the probe array may be functionalized such that certain of the probes are suitable for electrical sensing (e.g., recording) or stimulation, non-electrical sensing or stimulation (e.g., chemical sensing and/or release of biomolecules when activated), or a combination of electrical and non-electrical sensing or stimulation.

Abstract: A system and method for providing a position and orientation sensor package having a reduced size in at least one dimension is disclosed. The position and orientation sensor package includes a dielectric substrate and a first magneto-resistance sensor chip attached to the dielectric substrate, the first magneto-resistance sensor chip including at least one magneto-resistance sensor circuit. The position and orientation sensor package also includes a second magneto-resistance sensor chip attached to the dielectric substrate and positioned adjacent the first magneto-resistance sensor chip, the second magneto-resistance sensor chip including at least one magneto-resistance sensor circuit. The position and orientation sensor package is constructed such that the at least one magneto-resistance sensor circuit of the first magneto-resistance sensor chip is oriented in a different direction than the at least one magneto-resistance sensor circuit of the second magneto-resistance sensor chip.

Abstract: A filter package and method of manufacturing thereof is disclosed. The filter device package includes a first dielectric layer having an acoustic wave filter device attached thereto, the acoustic wave filter device comprising an active area and I/O pads. The filter device package also includes an adhesive positioned between the first dielectric layer and the acoustic wave filter device to secure the layer to the device, vias formed through the first dielectric layer and the adhesive to the I/O pads of the acoustic wave filter device, and metal interconnects formed in the vias and mechanically and electrically coupled to the I/O pads of the acoustic wave filter device to form electrical interconnections thereto, wherein an air cavity is formed in the adhesive between the acoustic wave filter device and the first dielectric layer, in a location adjacent the active area of the acoustic wave filter device.

Abstract: A system and method for providing a packaged electronics module having a dry film battery incorporated therein is disclosed. The packaged electronics module includes a first dielectric layer, at least one electronic component attached to or embedded in the first dielectric layer, a dry film battery formed on the first dielectric layer, and metal interconnects mechanically and electrically coupled to the at least one electronic component and the dry film battery to form electrical interconnections thereto. Electronic components in the form of a MEMS type sensor, semiconductor device and communications device may be included in the module along with the battery to provide a self-powered module capable of communicating with other like packaged electronics modules.

Abstract: A position and orientation system and method is provided. A magnetoresistance sensor is provided having a sensor array configured to measure magnetic fields and a metallic coil positioned within the magnetoresistance sensor. In certain embodiments, the magnetic coil may be used to generate a known magnetic field that, when measured by the sensor array, may be used to determine or update a calibration constant for the system.

Abstract: A system and method for providing a position and orientation sensor package having a reduced size in at least one dimension is disclosed. The position and orientation sensor package includes a dielectric substrate and a first magneto-resistance sensor chip attached to the dielectric substrate, the first magneto-resistance sensor chip including at least one magneto-resistance sensor circuit. The position and orientation sensor package also includes a second magneto-resistance sensor chip attached to the dielectric substrate and positioned adjacent the first magneto-resistance sensor chip, the second magneto-resistance sensor chip including at least one magneto-resistance sensor circuit. The position and orientation sensor package is constructed such that the at least one magneto-resistance sensor circuit of the first magneto-resistance sensor chip is oriented in a different direction than the at least one magneto-resistance sensor circuit of the second magneto-resistance sensor chip.

Abstract: Composite foams are provided including a metal template and a conformal atomic-scale film disposed over such metal template to form a 3-dimensional interconnected structure. The metal template includes a plurality of sintered interconnects, having a plurality of first non-spherical pores, a first non-spherical porosity, and a first surface-area-to-volume ratio. The conformal atomic-scale film has a plurality of second non-spherical pores, a second non-spherical porosity, and a second surface-area-to-volume ratio approximately equal to the first surface-area-to-volume ratio. The plurality of sintered interconnects has a plurality of dendritic particles and the conformal atomic-scale film includes at least one of a layer of graphene and a layer of hexagonal boron nitride.