Patents by Inventor Kazuaki Nakajima
Kazuaki Nakajima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120126574Abstract: A vehicle boundary layer air flow control structure is provided with a vehicle body and a side view mirror. The vehicle body includes an exterior contoured surface with an air flow deflector. The side view mirror is attached to the vehicle body to provide a diagonally rearward direction to be viewed from a driver's seat. The air flow deflector has a downward air flow guiding surface provided in a vehicle body region of the exterior contoured surface of the vehicle body along which an air flow heading toward the side view mirror passes. The downward air flow guiding surface extends in an air flow direction of the air flow with respect to the side view mirror to divert the air flow underneath the side view mirror.Type: ApplicationFiled: July 13, 2010Publication date: May 24, 2012Applicant: NISSAN MOTOR CO., LTD.Inventors: Satoshi Komiya, Kazuhito Sugimoto, Hirofumi Kondou, Yuichi Morinaka, Tomohiro Koyahata, Masato Inoue, Kenichiro Koizumi, Hitoshi Takagi, Yuji Ishihara, Kazuaki Nakajima
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Patent number: 8178062Abstract: In a reforming apparatus, for use in a fuel cell, for reforming a raw fuel into a hydrogen-rich reformed gas, a reformer generates the reformed gas from the raw fuel. A shift reactor reduces carbon monoxide contained in the reformed gas through a shift reaction. A selective oxidation unit reduces the carbon monoxide contained in the reformed gas that has passed through the shift reactor by performing selective oxidation on the carbon monoxide. A reforming reaction tube houses linearly the reformer, the shift reactor and the selective oxidation unit in this order. A combustion means produces combustion exhaust gas by combusting the raw fuel. An outer casing is placed around the reforming reaction tube, and the outer casing has a larger diameter than that of the reforming reaction tube. A heated flow passage through which the combustion exhaust gas passes to heat the reforming reaction tube is formed between the reforming reaction tube and the outer casing.Type: GrantFiled: September 26, 2008Date of Patent: May 15, 2012Assignees: Sanyo Electric Co., Ltd., Nippon Oil CorporationInventors: Akira Fuju, Masataka Kadowaki, Kazumi Kobayashi, Kazuaki Nakajima, Yasushi Sato, Ken Samura
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Publication number: 20120104795Abstract: A vehicle boundary layer air flow control structure is provided with a vehicle body and a side view mirror. The vehicle body includes an exterior contoured surface with an air flow deflector. The side view mirror is attached to the vehicle body to provide a diagonally rearward direction to be viewed from a driver's seat. The air flow deflector has an inward longitudinal air flow guiding surface provided in a vehicle body region of the exterior contoured surface of the vehicle body along which an air flow heading toward the side view mirror passes. The inward longitudinal air flow guiding surface extends in an air flow direction of the air flow with respect to the side view mirror to divert the air flow inward of the side view mirror with respect to a vehicle widthwise direction.Type: ApplicationFiled: July 13, 2010Publication date: May 3, 2012Applicant: NISSAN MOTOR CO., LTD.Inventors: Satoshi Komiya, Kazuhito Sugimoto, Hirofumi Kondou, Yuichi Morinaka, Tomohiro Koyahata, Masato Inoue, Kenichiro Koizumi, Hitoshi Takagi, Yuji Ishihara, Kazuaki Nakajima
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Publication number: 20120108211Abstract: A mobile communication system includes: a mobile terminal; plural base stations each of which can conduct communication with the mobile terminal; and a cooperative server that can conduct communication with the base station. The base station detects entrance and exit of the mobile terminal into and from an area covered by the base station and notifies the cooperative server of a detection result. The cooperative server acquires positional information on the mobile terminal from the notification, and stores a residence history of the mobile terminal based on the positional information and a script indicating a rule of a mode setting designated in each mobile terminal in history storing means. The cooperative server activates the script to determine a mode changing command in each mobile terminal based on the residence history and transmits the mode changing command to the base station.Type: ApplicationFiled: June 14, 2010Publication date: May 3, 2012Applicant: NEC CORPORATIONInventor: Kazuaki Nakajima
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Patent number: 8168522Abstract: An aspect of the present disclosure, there is provided a method for fabricating a semiconductor device, including, forming a gate insulating film on a semiconductor substrate, forming a metal film on the gate insulating film, depositing a metal-silicon compound film on the metal film without exposing the semiconductor substrate into atmosphere after forming the metal film, forming a silicon film on the metal-silicon compound film, and etching the metal film, the metal-silicon compound film, and the silicon film.Type: GrantFiled: March 5, 2010Date of Patent: May 1, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Kazuaki Nakajima
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Patent number: 8138553Abstract: A gate insulating film is formed on a main surface of a substrate in which an element isolation region is formed. A metal film is formed on the gate insulating film. A silicon film is formed on the metal film. A gate electrode of a MIS transistor composed of a stacked structure of the silicon film and metal film is formed on an element region and a high-resistance element composed of a stacked structure of the silicon film and metal film is formed on the element isolation region by patterning the silicon film and metal film. An acid-resistant insulating film is formed on the side of the gate electrode. The metal film of the high-resistance element is oxidized. A diffused layer of the MIS transistor is formed in the substrate.Type: GrantFiled: January 12, 2010Date of Patent: March 20, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Kazuaki Nakajima
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Publication number: 20110298055Abstract: In a semiconductor substrate on which are formed an N-type MOS transistor and a P-type MOS transistor, the gate electrode of the N-type MOS transistor comprises a tungsten film, which makes contact with a gate insulation film, and the gate electrode of the P-type MOS transistor comprises a tungsten film, which makes contact with a gate insulation film, and the concentration of carbon contained in the former tungsten film is less than the concentration of carbon contained in the latter tungsten film.Type: ApplicationFiled: August 10, 2011Publication date: December 8, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Kazuaki Nakajima, Kyoichi Suguro
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Publication number: 20110280128Abstract: In switching of a conference server in a group conference system, switching of a session of each terminal device is completed smoothly in as a short time period as possible without imposing loads on a call control server. A conference server 121 connected to a call control server 110 which relays a request for call control of a group conference system and a plurality of terminal devices 130, including a session shift control unit 223 which determines an order of a request for call control of each terminal device which request is related to cut-off from a target from which a session is to be shifted and connection to a session shifting destination according to information related to session generation of each terminal device and a conference condition and determines timing of call control based on a load condition of the call control server, and a session shift instructing unit 224 which transmits a request for call control to the call control server according to the determined order and timing.Type: ApplicationFiled: June 29, 2009Publication date: November 17, 2011Applicant: NEC CORPORATIONInventor: Kazuaki Nakajima
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Patent number: 8030711Abstract: A method of manufacturing a semiconductor device, comprises: forming a high dielectric gate insulating film in an nMIS formation region and a pMIS formation region of a semiconductor substrate; forming a first metal film on the high dielectric gate insulating film, the first metal film; removing the first metal film in the nMIS formation region; forming a second metal film on the high dielectric gate insulating film of the nMIS formation region and on the first metal film of the pMIS formation region; and processing the first metal film and the second metal film. The high dielectric gate insulating film has a dielectric constant higher than a dielectric constant of silicon oxide. The first metal film does not contain silicon and germanium. The second metal film contains at least one of silicon and germanium.Type: GrantFiled: December 10, 2009Date of Patent: October 4, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Kazuaki Nakajima
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Patent number: 8017466Abstract: In a semiconductor substrate on which are formed an N-type MOS transistor and a P-type MOS transistor, the gate electrode of the N-type MOS transistor comprises a tungsten film, which makes contact with a gate insulation film, and the gate electrode of the P-type MOS transistor comprises a tungsten film, which makes contact with a gate insulation film, and the concentration of carbon contained in the former tungsten film is less than the concentration of carbon contained in the latter tungsten film.Type: GrantFiled: November 10, 2009Date of Patent: September 13, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Kazuaki Nakajima, Kyoichi Suguro
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Publication number: 20110187912Abstract: A solid state imaging device according to an embodiment includes a light sensing part which conducts photoelectric conversion on incident light. The solid state imaging device includes a ferroelectric layer including an organic compound on a surface of the light sensing part on which light is incident. The solid state imaging device includes a transparent electrode formed on the ferroelectric layer.Type: ApplicationFiled: January 31, 2011Publication date: August 4, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yusuke ARAYASHIKI, Kazuaki Nakajima
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Patent number: 7989896Abstract: A method of fabricating a semiconductor device according to one embodiment includes: laying out a first region, a second region, a third region and a fourth region on a semiconductor substrate by forming an element isolation region in the semiconductor substrate; forming a first insulating film on the first region and the second region; forming a first semiconductor film on the first insulating film; forming a second insulating film and an aluminum oxide film thereon on the fourth region after forming of the first semiconductor film; forming a third insulating film and a lanthanum oxide film thereon on the third region after forming of the first semiconductor film; forming a high dielectric constant film on the aluminum oxide film and the lanthanum oxide film; forming a metal film on the high dielectric constant film; forming a second semiconductor film on the first semiconductor film and the metal film; and patterning the first insulating film, the first semiconductor film, the second insulating film, the alType: GrantFiled: November 4, 2009Date of Patent: August 2, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Tomonori Aoyama, Seiji Inumiya, Kazuaki Nakajima, Takashi Shimizu
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Patent number: 7968956Abstract: A semiconductor device includes a semiconductor substrate, a p-channel MIS transistor formed on the substrate, the p-channel transistor having a first gate dielectric formed on the substrate and a first gate electrode layer formed on the first dielectric, and an n-channel MIS transistor formed on the substrate, the n-channel transistor having a second gate dielectric formed on the substrate and a second gate electrode layer formed on the second dielectric. A bottom layer of the first gate electrode layer in contact with the first gate dielectric and a bottom layer of the second gate electrode layer in contact with the second gate dielectric have the same orientation and the same composition including Ta and C, and a mole ratio of Ta to a total of C and Ta, (Ta/(Ta+C)), is larger than 0.5.Type: GrantFiled: February 19, 2009Date of Patent: June 28, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Kosuke Tatsumura, Masakazu Goto, Reika Ichihara, Masato Koyama, Shigeru Kawanaka, Kazuaki Nakajima
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Patent number: 7952148Abstract: A semiconductor device according to the embodiments comprises a gate insulator formed on a substrate, the gate insulator including a high-dielectric film in whole or part, a reaction film including a first metal on the gate insulator; a metal film including a second metal on the reaction film; and a film including Si formed on the metal film.Type: GrantFiled: January 14, 2011Date of Patent: May 31, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Kazuaki Nakajima
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Publication number: 20110101468Abstract: A semiconductor device according to the embodiments comprises a gate insulator formed on a substrate, the gate insulator including a high-dielectric film in whole or part, a reaction film including a first metal on the gate insulator; a metal film including a second metal on the reaction film; and a film including Si formed on the metal film.Type: ApplicationFiled: January 14, 2011Publication date: May 5, 2011Applicant: Kabushiki Kaisha ToshibaInventor: Kazuaki Nakajima
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Patent number: 7892913Abstract: A method of manufacturing a semiconductor device comprises: forming a gate insulator on a substrate, the gate insulator including a high-dielectric film in whole or part; forming a first metal film on the gate insulator; forming a second metal film on the first metal film; and forming a reaction film between the gate insulator and the first metal film by letting the high-dielectric film and the first metal film react with each other through a thermal treatment.Type: GrantFiled: March 13, 2009Date of Patent: February 22, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Kazuaki Nakajima
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Publication number: 20100288995Abstract: A semiconductor memory device includes: a lower electrode including a plurality of projections formed on a top surface thereof; an oxide film covering the top surface and made of an oxide of a same metal as a metal contained in the lower electrode; and a resistance variable film provided on the oxide film and being in contact with the oxide film, the projections being buried in the oxide film, and a lower layer portion of the resistance variable film having an oxygen concentration lower than an oxygen concentration of a portion other than the lower layer portion of the resistance variable film.Type: ApplicationFiled: March 19, 2010Publication date: November 18, 2010Inventors: Yoshio Ozawa, Katsuyuki Sekine, Kazuaki Nakajima
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Publication number: 20100291765Abstract: An aspect of the present disclosure, there is provided a method for fabricating a semiconductor device, including, forming a gate insulating film on a semiconductor substrate, forming a metal film on the gate insulating film, depositing a metal-silicon compound film on the metal film without exposing the semiconductor substrate into atmosphere after forming the metal film, forming a silicon film on the metal-silicon compound film, and etching the metal film, the metal-silicon compound film, and the silicon film.Type: ApplicationFiled: March 5, 2010Publication date: November 18, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Kazuaki Nakajima
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Patent number: 7820476Abstract: A method for manufacturing a semiconductor device includes: forming a first region and a second region at a main surface of a semiconductor substrate; forming a gate insulating film containing Hf or Zr and oxygen on the first region and the second region; forming a first metallic film on the gate insulating film; forming a second metallic film on the first metallic film; removing a portion of the second metallic film; forming a third metallic film on the second metallic film and a portion of the first metallic film exposed by removing the portion of the second metallic film; and thermally treating so that constituent elements of the second metallic film is diffused into the gate insulating film via the first metallic film.Type: GrantFiled: October 9, 2008Date of Patent: October 26, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Kazuaki Nakajima
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Patent number: 7768076Abstract: A semiconductor device has an n-channel MISFET having first diffusion layers formed in a first region of a surface portion of a semiconductor substrate so as to sandwich a first channel region therebetween, a first gate insulating film formed on the first channel region, and a first gate electrode including a first metal layer formed on the first gate insulating film, and a first n-type polysilicon film formed on the first metal layer, and a p-channel MISFET having second diffusion layers containing boron as a dopant and formed in a second region of the surface portion of the semiconductor substrate so as to sandwich a second channel region therebetween, a second gate insulating film formed on the second channel region, and a second gate electrode including a second metal layer containing nitrogen or carbon and formed on the second gate insulating film and a second n-type polysilicon film formed on the second metal layer and having a boron concentration of not more than 5×1019 cm?3 in a portion adjacent an inType: GrantFiled: May 1, 2008Date of Patent: August 3, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Kazuaki Nakajima