Patents by Inventor Kazuaki Nakajima

Kazuaki Nakajima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080138969
    Abstract: A method of manufacturing a semiconductor device having a MOSFET of a first conductivity type and a MOSFET of a second conductivity type different from the first conductivity type formed on a semiconductor substrate, the method has: forming a gate insulating film; forming a first gate electrode layer, and forming a second gate electrode layer; forming a first metal containing layer on said first gate electrode layer and said second gate electrode layer; forming a second metal containing layer for preventing diffusion of a metal on said first metal containing layer; forming a third metal containing layer on said second gate electrode layer from which said first metal containing layer and said second metal containing layer are selectively removed, the third metal containing layer having a thickness different from the thickness of said first metal containing layer in a case where the third metal containing layer contains the same metal or alloy as the metal or alloy contained in said first metal containing layer
    Type: Application
    Filed: November 30, 2007
    Publication date: June 12, 2008
    Inventors: Akio Kaneko, Motoyuki Sato, Katsuyuki Sekine, Tomohiro Saito, Kazuaki Nakajima, Tomonori Aoyama
  • Publication number: 20080135936
    Abstract: The method of manufacturing a semiconductor device includes: forming a gate insulating film on a semiconductor substrate; forming a thin silicon layer on the gate insulating film; and forming a metal film on the thin silicon layer, having a work function at the interface with respect to the gate insulating film of a value within a predetermined range.
    Type: Application
    Filed: November 30, 2007
    Publication date: June 12, 2008
    Inventor: Kazuaki NAKAJIMA
  • Patent number: 7354819
    Abstract: A semiconductor device is disclosed, which comprises a silicon substrate, a complementary MISFET circuit, an insulation film formed on the silicon substrate, a first contact hole formed in the insulation film, a first metal silicide layer formed on the bottom of the first contact hole, the first metal silicide layer being provided by a reaction of the n-channel impurity diffused region of the n-channel MISFET with a first metal, a second contact hole formed in the insulation film, a second metal silicide layer formed on the bottom of the second contact hole, the second metal silicide layer being provided by a reaction of the p-channel impurity diffused region of the p-channel MISFET with a second metal, and a work function of the second metal silicide layer being higher than that of the first metal silicide layer.
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: April 8, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuaki Nakajima, Kyoichi Suguro
  • Publication number: 20070278587
    Abstract: This disclosure concerns a semiconductor device comprising a semiconductor substrate; a gate dielectric film provided on the semiconductor substrate and containing Hf, Si, and O or containing Zr, Si and O; a gate electrode of an n-channel FET provided on the gate dielectric film, the gate electrode being made of nickel silicide containing nickel at a higher content than silicon; an aluminum layer provided at a bottom portion of the gate electrode of the n-channel FET; and a gate electrode of a p-channel FET provided on the gate dielectric film, the gate electrode being made of nickel silicide containing nickel at a higher content than silicon.
    Type: Application
    Filed: May 10, 2007
    Publication date: December 6, 2007
    Inventors: Tomonori Aoyama, Tomohiro Saito, Katsuyuki Sekine, Kazuaki Nakajima, Motoyuki Sato, Takuya Kobayashi
  • Publication number: 20070278588
    Abstract: A semiconductor device manufacturing method has forming a gate insulation film on a silicon substrate having an nMOS transistor region and a pMOS transistor region, forming a first metal film on the gate insulation film and thereby forming a gate electrode of the nMOS transistor, removing the first metal film in the pMOS transistor region, forming a silicon film on the first metal film in the nMOS transistor region and on the gate insulation film in the pMOS transistor region, forming a second metal film having a work function higher than that of the first metal film on the silicon film and causing reaction between the second metal film and the silicon film and thereby forming a metal silicon compound film which serves as a gate electrode of the pMOS transistor.
    Type: Application
    Filed: May 30, 2007
    Publication date: December 6, 2007
    Inventor: Kazuaki Nakajima
  • Patent number: 7269618
    Abstract: A server system includes a data storage section, HTTP server, back-end server, difference update instruction issuing sections, event management section, and real-time communication/transmission control section. The data storage section stores data. The HTTP server responds to an information transmission request sent from a client via the Internet, extracts requested information from the data storage section, and sends the information to the client. The back-end server sends an event associated with updating of the requested information. The difference update instruction issuing sections receive the event from the back-end server and issue difference update instructions to update the requested information. The event management section selects one of the difference update instruction issuing sections on the basis of the initial state associated with the requested information, and notifies the selected initial data instruction issuing section of the event.
    Type: Grant
    Filed: April 12, 2002
    Date of Patent: September 11, 2007
    Assignee: NEC Corporation
    Inventor: Kazuaki Nakajima
  • Publication number: 20070184592
    Abstract: A gate insulating film is formed on a silicon substrate, a conductor film constituting a gate electrode is formed on the gate insulating film by a formation method using an organic material, and the silicon substrate, on which the conductor film is formed, is heated in a mixed atmosphere of steam which is an oxidizing atmosphere and hydrogen which is a reducing atmosphere with a partial pressure ratio of hydrogen to steam which is set such that carbon is oxidized and that a metal material constituting the conductor film is reduced.
    Type: Application
    Filed: January 31, 2007
    Publication date: August 9, 2007
    Inventor: Kazuaki Nakajima
  • Patent number: 7232751
    Abstract: According to the manufacturing method of the semiconductor device of the present invention, an oxide film is formed on a metal film formed on a main surface of a semiconductor substrate by exposing the metal film to the oxidizing gas. The oxide film is then reduced in a reducing atmosphere, and a protection film is formed on the surface of the metal film reduced in the reducing step. In this manner, the damage to the surface of the metal film can be prevented.
    Type: Grant
    Filed: February 2, 2005
    Date of Patent: June 19, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasushi Akasaka, Kazuaki Nakajima, Kiyotaka Miyano, Kyoichi Suguro
  • Publication number: 20070105317
    Abstract: A method of manufacturing a semiconductor device according to an aspect of the present invention comprises a step of forming a gate insulating layer on a semiconductor substrate, a step of forming a first metal layer on the gate insulating layer, a step of forming a second metal layer including elements for use in work function modulation on the first metal layer, a step of forming a cap layer made of a material having a melting point higher than that of the second metal layer on the second metal layer, and a step of precipitating the elements at an interface between the gate insulating layer and the first metal layer by thermal treatment.
    Type: Application
    Filed: March 20, 2006
    Publication date: May 10, 2007
    Inventor: Kazuaki Nakajima
  • Publication number: 20070099370
    Abstract: A method for manufacturing a semiconductor device includes forming a gate insulating film on a semiconductor substrate, and forming a gate electrode comprising a metal semiconductor compound layer and having a predetermined gate length on the gate insulating film, the forming the gate electrode including forming a polycrystalline semiconductor film having an average grain diameter below a specific size depending on the predetermined gate length and including at least one of silicon and germanium, the average grain diameter of the semiconductor film being 5 nm or more and 90 nm or less, forming a metal film on the semiconductor film, and converting whole of the semiconductor film into the metal semiconductor compound layer by reacting the semiconductor film and the metal film by heat treatment.
    Type: Application
    Filed: September 21, 2006
    Publication date: May 3, 2007
    Inventors: Kazuaki Nakajima, Tomohiro Saito
  • Publication number: 20070099385
    Abstract: The present invention provides a method of manufacturing a semiconductor device, comprising forming an electrode pattern made of silicon on a gate insulating film in an n-MOS region and a p-MOS region of a semiconductor substrate, masking the n-MOS region including the first electrode pattern with a first insulating film pattern, forming a first metal film made of platinum all over the surface, forming a gate electrode consisting of a platinum silicide in the p-MOS region, forming an silicon oxide film on the surface of the gate electrode by oxidation, dissolving away a non-reacting Pt film, removing the first insulating film pattern, masking the p-MOS region including the electrode pattern with a second insulating film pattern, forming a second metal film made of europium all over the surface, and forming a gate electrode consisting of a europium silicide in the n-MOS region.
    Type: Application
    Filed: October 2, 2006
    Publication date: May 3, 2007
    Inventors: Kazuaki Nakajima, Atsushi Yagishita
  • Publication number: 20070099363
    Abstract: There are provided steps of: forming a gate insulating film on a semiconductor substrate; sequentially forming a first gate electrode material film, a first insulating film, a second gate electrode material film, which is thinner than the first gate electrode material film, on the gate insulating film, and patterning these films and the gate insulating film, thereby forming a gate electrode; forming a first metal film at least on the second gate electrode material film of the gate electrode and causing the first metal film to react, thereby changing the second gate electrode material film of the gate electrode to a first reaction layer; removing the first reaction layer on the gate electrode; forming an interlayer insulating film on the entire surface and flattening the interlayer insulating film until the first gate electrode material film of the gate electrode is exposed; forming a second metal film on the entire surface and causing the second metal film to react with the first gate electrode material film
    Type: Application
    Filed: September 14, 2006
    Publication date: May 3, 2007
    Inventor: Kazuaki Nakajima
  • Publication number: 20070090427
    Abstract: A method of manufacturing a semiconductor device, comprises: forming a high dielectric gate insulating film in an nMIS formation region and a pMIS formation region of a semiconductor substrate; forming a first metal film on the high dielectric gate insulating film, the first metal film; removing the first metal film in the nMIS formation region; forming a second metal film on the high dielectric gate insulating film of the nMIS formation region and on the first metal film of the pMIS formation region; and processing the first metal film and the second metal film. The high dielectric gate insulating film has a dielectric constant higher than a dielectric constant of silicon oxide. The first metal film does not contain silicon and germanium. The second metal film contains at least one of silicon and germanium.
    Type: Application
    Filed: October 25, 2006
    Publication date: April 26, 2007
    Inventor: Kazuaki Nakajima
  • Patent number: 7172955
    Abstract: A semiconductor device comprises an n-type MIS transistor comprising a first gate insulating film and a first gate electrode including an MSix film formed on the first gate insulating film, where M represents a metal element selected from tungsten and molybdenum and x is greater than 1, i.e., x>1; and a p-type MIS transistor comprising a second gate insulating film and a second gate electrode including an MSiy film formed on the second gate insulating film, where y is not less than 0 and less than 1, i.e., 0?y<1.
    Type: Grant
    Filed: November 28, 2005
    Date of Patent: February 6, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kouji Matsuo, Kazuaki Nakajima
  • Publication number: 20070026597
    Abstract: A method of manufacturing a semiconductor device including a MOS transistor includes: forming a gate electrode on a semiconductor substrate via a gate insulating film; performing ion implantation on the semiconductor substrate using the gate electrode as a mask, and performing a heat treatment, thereby forming a diffusion layer in the semiconductor substrate; depositing an insulating film on the gate electrode and the semiconductor substrate to bury the insulating film in the gate electrode; flattening the insulating film to expose an upper surface of the gate electrode; selectively forming a metal film only on the gate electrode; and changing a material of the gate electrode to a metal compound using a metal in the metal film.
    Type: Application
    Filed: July 28, 2006
    Publication date: February 1, 2007
    Inventor: Kazuaki Nakajima
  • Publication number: 20060273413
    Abstract: There are provided: a semiconductor substrate including first and second device regions isolated by device isolation regions; a first gate insulating film of a high-k material formed in the first device region; a first gate electrode formed on the first gate insulating film; first source and drain regions formed at both sides of the first gate electrode in the first device region; a second gate insulating film of a high-k material which is different from the high-k material of the first gate insulating film, the second gate insulating film being formed in the second device region; a second gate electrode formed on the second gate insulating film; and second source and drain regions formed at both sides of the second gate electrode in the second device region.
    Type: Application
    Filed: July 21, 2005
    Publication date: December 7, 2006
    Inventors: Motoyuki Sato, Katsuyuki Sekine, Kazuaki Nakajima, Tomohiro Saito, Kazuhiro Eguchi, Atsushi Yagishita
  • Patent number: 7139858
    Abstract: A server for carrying out synchronization control, includes (a) at least one event receiver for receiving an event, (b) a memory storing therein distribution schedule information including a plurality of schedule data therein, each of the schedule data including (b1) a timing at which a channel driver controls a media server, (b2) a content of how the channel driver controls the media server, and (b3) a timing type indicating which one of a time and the event the timing is defined by, and (c) a controller which detects whether a timing is established for each of the schedule data included in the distribution schedule information, and transmits a signal to the channel driver, the signal being indicative of a control associated with the established timing.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: November 21, 2006
    Assignee: NEC Corporation
    Inventor: Kazuaki Nakajima
  • Publication number: 20060237816
    Abstract: In a semiconductor substrate on which are formed an N-type MOS transistor and a P-type MOS transistor, the gate electrode of the N-type MOS transistor comprises a tungsten film, which makes contact with a gate insulation film, and the gate electrode of the P-type MOS transistor comprises a tungsten film, which makes contact with a gate insulation film, and the concentration of carbon contained in the former tungsten film is less than the concentration of carbon contained in the latter tungsten film.
    Type: Application
    Filed: April 3, 2006
    Publication date: October 26, 2006
    Inventors: Kazuaki Nakajima, Kyoichi Suguro
  • Patent number: 7045448
    Abstract: According to the present invention, there is provided a semiconductor device, comprising: a gate electrode formed on a substrate via a gate insulating film by using a first silicide film; diffusion layers formed in a surface portion of said substrate so as to be positioned at two ends of a channel region below said gate electrode, and having a second silicide film on surfaces thereof; a first insulating film formed on said second suicide film of said diffusion layers; and a second insulating film continuously formed on said first insulating film and said gate electrode, wherein a total film thickness of said first and second insulating films on said second silicide film is larger than a film thickness of said second insulating film on said gate electrode.
    Type: Grant
    Filed: November 3, 2004
    Date of Patent: May 16, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazuaki Nakajima
  • Patent number: 7041584
    Abstract: An aspect of the present invention provides a method of manufacturing a semiconductor device, including, forming an insulating film on a silicide layer formed at the surface of a silicon semiconductor substrate, etching the insulating film to form a contact hole in which the silicide layer is exposed, forming a metal nitride film on the bottom and side wall of the contact hole, carrying out a first heating process at 600° C. or lower on the substrate, carrying out, during the first heating process, a second heating process for 10 msec or shorter with light whose main wavelength is shorter than a light absorbing end of silicon, forming a contact conductor in the contact hole after the second heating process, and forming, on the insulating film, wiring that is electrically connected to the substrate through the contact conductor.
    Type: Grant
    Filed: June 16, 2004
    Date of Patent: May 9, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Kazuaki Nakajima, Yoshitaka Tsunashima, Takayuki Ito, Kyoichi Suguro