Abstract: The present invention has an arrangement that includes a Y decoder that selects a main bit line MBL to which sub bit lines SBL connected to memory cells MC are connected and selects main bit lines MBL adjacent to the selected main bit line MBL, and a YRST transistor that connects the adjacent main bit lines MBL to a given interconnection line and set these main bit lines to a given voltage. With this structure, it is possible to restrain noise from the adjacent main bit lines MBL to the minimum and prevent degradation of the voltage margin.

Abstract: A semiconductor device of the present invention includes a booster circuit 20 that boosts a selected word line (WL) to a given voltage higher than a power supply voltage and a charge pump circuit that retains the boosted word line (WL) at the first given voltage. When the booster circuit boosts the word line, the voltage level is degraded as the time goes. However, it is possible to program the memory cell and read out thereof properly by retaining the voltage of the word line with the charge pump circuit.

Abstract: A semiconductor device is provided that can perform simultaneous writing of a large number of bits, without an increase in chip size. This semiconductor device includes: a write data bus via which data are written into memory cells; a read data bus via which the data are read from the memory cells; a first write amplifier that writes data into the memory cells via the read data bus at the time of high-speed writing; a second write amplifier that writes data into the memory cells via the write data bus at the time of high-speed writing; a first sense amplifier that reads verified data from the memory cells via the read data bus; and a second sense amplifier that reads verified data from the memory cells via the write data bus.

Abstract: A semiconductor device includes a first cascode circuit having a first current mirror amplifying a reference current flowing through a data line of a reference cell, and a second current mirror generating a first potential from an amplified reference current; and a second cascode circuit having a third current mirror amplifying a core current flowing through a data line of a core cell, and a transistor receiving a gate voltage corresponding to the amplified reference current and generating a second potential based on a difference between an amplified core cell current and the amplified reference current. Since the second potential is generated by the difference between the core cell current and the reference cell current, the second potential swings in the full range of the ground power supply voltage to the ground potential, and the range of the amplitude of the power supply voltage can be efficiently utilized. Sensing is enabled for a fine current margin.

Abstract: The precharge circuit is provided for precharging, before programming the data, the voltage of the source line ARVSS commonly connected to the memory cells provided in the same sector. The voltage of the source line ARVSS of the memory cell MC is precharged before programming the data, and the voltage of the source line ARVSS of the memory cell MC is not lowered at the time of programming the data, even if the data programming period is shortened. It is thus possible to prevent the leak current during the programming and program the data into the memory cell MC optimally.

Abstract: A sector protection circuit of the invention has a non-volatile storage section storing data indicating sector protection/unprotection for each sector or each sector group, and a volatile storage section storing data indicating sector protection/unprotection for each sector or each sector group. Normally, each sector or sector group can be protected when data indicative of sector or sector group protection is stored in at least one of the non-volatile storage section and the volatile storage section. When a given command is received in the above normal state, data only in the volatile storage section is enabled.

Abstract: A flash memory having a nonvolatile memory cell, includes a plurality of banks each having a plurality of sectors, an erasing voltage generator circuit and a writing voltage generator circuit, wherein while an applying an erase pulse to a sector to be erased in a first bank, an erasing control is performed by, a pre-writing control is concurrently performed by applying a writing pulse to a sector to be erased in a second bank. At the time when erasing control of the sector to be erased in a first bank is finished, pre-writing control of the sector to be erased in a second bank is finished or partially finished, and thus the time required for erasing operations of the first and the second bank can be reduced.

Abstract: A semiconductor memory including an address change detection unit for detecting a change of an address and outputting an address change detection signal, a selection unit for selectively switching the polling data and the read data by a polling signal, and outputting its data to the output buffer, and a delay unit for inhibiting the polling signal from being transferred to the selection unit while the address change detection signal is activated. When the polling signal changes while a sense amplifier senses data, the logic level of a signal output from the output buffer is inhibited from being changed. This prevents any malfunction caused by output noise generated during the data sense operation of the sense amplifier.

Abstract: The non-volatile semiconductor memory of the present invention is comprised of: a memory cell array including a plurality of memory cells which is disposed at intersections of a plurality of bit lines and word lines and are connected to said bit lines; and a writing circuit which receives an address signal and supplies a bit line voltage to the bit line connected to the memory cell selected with the address signal during writing operation. The writing circuit changes, based on the address signal, a level of the bit line voltage depending on a position of the selected memory cell in the memory cell array. The writing circuit operates, based on the inputted writing address, to further increase a level of the bit line voltage supplied to the memory cell as the wiring distance via the bit line from the output end of the bit line voltage of the writing circuit thereto is longer, fluctuation of writing speed in each memory cell of a memory cell array is reduced.

Abstract: A flash memory having a nonvolatile memory cell, includes a plurality of banks each having a plurality of sectors, an erasing voltage generator circuit and a writing voltage generator circuit, wherein while an applying an erase pulse to a sector to be erased in a first bank, an erasing control is performed by, a pre-writing control is concurrently performed by applying a writing pulse to a sector to be erased in a second bank.

Abstract: A signal delay circuit (100) is provided for inhibiting an output control signal (/OE), which is externally input, from transferring to an output buffer (6) for a predetermined period after an address change. While a sense amplifier (1) senses data in the predetermined period after the address changes, the logic level of a signal (OUT) output from the output buffer (6) is inhibited from being inverted. This prevents any malfunction caused by output noise generated during the data sense operation of the sense amplifier (1).

Abstract: A signal delay circuit (100) is provided for inhibiting an output control signal (/OE), which is externally input, from transferring to an output buffer (6) for a predetermined period after an address changes. While a sense amplifier (1) senses data in the predetermined period after the address changes, the logic level of a signal (OUT) output from the output buffer (6) is inhibited from being inverted. This prevents any malfunction caused by output noise generated during the data sense operation of the sense amplifier (1).

Abstract: The non-volatile semiconductor memory of the present invention is comprised of: a memory cell array including a plurality of memory cells which is disposed at intersections of a plurality of bit lines and word lines and are connected to said bit lines; and a writing circuit which receives an address signal and supplies a bit line voltage to the bit line connected to the memory cell selected with the address signal during writing operation. The writing circuit changes, based on the address signal, a level of the bit line voltage depending on a position of the selected memory cell in the memory cell array. The writing circuit operates, based on the inputted writing address, to further increase a level of the bit line voltage supplied to the memory cell as the wiring distance via the bit line from the output end of the bit line voltage of the writing circuit thereto is longer, fluctuation of writing speed in each memory cell of a memory cell array is reduced.

Abstract: The present invention provides a dummy cell that provides a dummy programming level and a dummy erasing level which are set such as to give “fail” results during verify operations under ordinary conditions and “pass” results when noises affect verify operations, thereby ascertaining correct programming or erase operation for flash memories.

Abstract: The present invention provides a dummy cell that provides a dummy programming level and a dummy erasing level which are set such as to give “fail” results during verify operations under ordinary conditions and “pass” results when noises affect verify operations, thereby ascertaining correct programming or erase operation for flash memories.

Abstract: The present invention is a flash memory, wherein when erasing a plurality of sectors an erasure process of applying a normal erasure stress to one sector is performed, while at the same time, a pre-erasure process of applying a pre-erasure stress, that is weaker than the normal erasure stress, to the other sectors to be erased is performed. By performing a pre-erasure process to the other sectors while the normal erasure process is being performed, it is possible to shorten the following erasure processing for the other sectors.

Abstract: In addition to the capacitors connected conventionally in parallel to an output of a bit line at the source of a reference cell 30, a capacitor C20 is provided. Further, a capacitor C21 that is provided which is connected during data reading operation and program verification operation. This capacitor C21 is disconnected during erase verification operation. Further, a capacitor C22 is provided which is connected during the program verification operation. Accordingly, it is possible to increase or decrease the electric potential of the signal SAREF output from the reference cell 30 during program verification operation and erase verification operation.

Abstract: The present invention is a flash memory, wherein when erasing a plurality of sectors an erasure process of applying a normal erasure stress to one sector is performed, while at the same time, a pre-erasure process of applying a pre-erasure stress, that is weaker than the normal erasure stress, to the other sectors to be erased is performed. By performing a pre-erasure process to the other sectors while the normal erasure process is being performed, it is possible to shorten the following erasure processing for the other sectors.

Abstract: The present invention is a memory circuit having memory cell array transistors with floating gates, wherein the boost ratio of the boosted voltage generating circuit is varied so that the boosted voltage level for driving wordlines during reading becomes constant depending on the power source voltage level. Specifically, when the power source voltage decreases, the boost ratio increases and when the power source voltage increases, the boost ratio decreases. As a result, the boosted voltage for driving wordlines during reading can be maintained within a prescribed range and appropriate read operations can be ensured.

Abstract: An output driver circuit provided with a pull-up pMOS transistor and a pull-down nMOS transistor also includes an nMOS transistor connected between the pMOS transistor and an output. A step-up unit is provided for stepping up a gate voltage of the nMOS transistor when high data is to be output.