Patents by Inventor Kazuhiko Kajigaya

Kazuhiko Kajigaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10998046
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. One method includes determining whether to access a first memory cell of a first memory cell array or a second memory cell of a second memory cell array, where a first digit line coupled to the first memory cell is coupled to a paging buffer register including a sense amplifier. The method further includes operating a transfer gate based at least in part on determining to read the second memory cell of the second memory cell array, where the transfer gate is configured to selectively couple a second digit line coupled to the second memory cell to the paging buffer register through the first digit line.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Kazuhiko Kajigaya
  • Publication number: 20210018952
    Abstract: Provided is a semiconductor module which enables a memory bandwidth to be widened, and which enables data transfer efficiency to be improved by reducing power consumption. A semiconductor module 1 comprises: an interposer 10; and a processing unit 20 which has a plurality of processing unit main bodies 21 arrayed to be side by side with each other in a first direction F1 along the plate surface of the interposer 10, and which is placed on the interposer 10 so as to be electrically connected to the interposer 10. The processing unit main bodies 21 are provided with a plurality of subset units 22 each including: one arithmetic unit 23 including at least one core 25; and one memory unit 24 that is configured from a stacked-type RAM module and that is disposed to be side by side with the calculation unit 23 in the first direction F1. The plurality of subset units 22 are arrayed to be side by side with each other in a second direction F2 that intersects with the first direction F1.
    Type: Application
    Filed: June 2, 2017
    Publication date: January 21, 2021
    Inventors: Kazuhiko KAJIGAYA, Takao ADACHI
  • Publication number: 20200379655
    Abstract: Methods, systems, and devices for operating a memory device are described. One method includes caching data of a memory cell at a sense amplifier of a row buffer upon performing a first read of the memory cell; determining to perform at least a second read of the memory cell after performing the first read of the memory cell; and reading the data of the memory cell from the sense amplifier for at least the second read of the memory cell.
    Type: Application
    Filed: August 20, 2020
    Publication date: December 3, 2020
    Inventor: Kazuhiko Kajigaya
  • Publication number: 20200363978
    Abstract: Apparatuses and methods for controlling word lines and sense amplifiers in a semiconductor device are described.
    Type: Application
    Filed: August 6, 2020
    Publication date: November 19, 2020
    Applicant: Micron Technology, Inc.
    Inventor: Kazuhiko Kajigaya
  • Patent number: 10839933
    Abstract: A semiconductor device is provided with normal memory cells constituted so as to store user data, reference memory cells constituted so as to generate a reference signal for reading out the normal memory cells, and a control circuit that carries out a defect detecting operation for detecting whether or not the reference memory cell and data stored in the reference memory cell are coincident with expected values on the stored data read out from the reference memory cells. Moreover, it is also provided with a control circuit for executing a defect correcting operation for correcting data to be stored in the reference memory cells that are detected as defective. Furthermore, it is also provided with a control circuit that is configured so as to cut off the reference memory cell detected as defective from the sense amplifier.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Kazuhiko Kajigaya
  • Patent number: 10776016
    Abstract: Methods, systems, and devices for operating a memory device are described. One method includes caching data of a memory cell at a sense amplifier of a row buffer upon performing a first read of the memory cell; determining to perform at least a second read of the memory cell after performing the first read of the memory cell; and reading the data of the memory cell from the sense amplifier for at least the second read of the memory cell.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: September 15, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Kazuhiko Kajigaya
  • Patent number: 10747463
    Abstract: Apparatuses and methods for controlling word lines and sense amplifiers in a semiconductor device are described.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: August 18, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Kazuhiko Kajigaya
  • Patent number: 10522222
    Abstract: A device with error correction is provided. The device includes a plurality of memory cells, and reference read write circuit, a plurality of sense amplifiers, and an error-correction code control block. The reference read write circuit is configured to generate a reference voltage in response to data stored in at least one of the plurality of memory cells. A plurality of sense amplifiers are each coupled to a respective memory cell of the plurality of memory cells. An error-correction code (ECC) control block may output an error signal when the ECC control block detects that it is unable to correct error data in one or more respective memory cells. The reference read write circuit may overwrite data in the at least one of the plurality of memory cells in response to the error signal.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: December 31, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Kazuhiko Kajigaya
  • Publication number: 20190362790
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. One method includes determining whether to access a first memory cell of a first memory cell array or a second memory cell of a second memory cell array, where a first digit line coupled to the first memory cell is coupled to a paging buffer register including a sense amplifier. The method further includes operating a transfer gate based at least in part on determining to read the second memory cell of the second memory cell array, where the transfer gate is configured to selectively couple a second digit line coupled to the second memory cell to the paging buffer register through the first digit line.
    Type: Application
    Filed: June 13, 2019
    Publication date: November 28, 2019
    Inventor: Kazuhiko Kajigaya
  • Publication number: 20190304564
    Abstract: A semiconductor device is provided with normal memory cells constituted so as to store user data, reference memory cells constituted so as to generate a reference signal for reading out the normal memory cells, and a control circuit that carries out a defect detecting operation for detecting whether or not the reference memory cell and data stored in the reference memory cell are coincident with expected values on the stored data read out from the reference memory cells. Moreover, it is also provided with a control circuit for executing a defect correcting operation for correcting data to be stored in the reference memory cells that are detected as defective. Furthermore, it is also provided with a control circuit that is configured so as to cut off the reference memory cell detected as defective from the sense amplifier.
    Type: Application
    Filed: June 18, 2019
    Publication date: October 3, 2019
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: KAZUHIKO KAJIGAYA
  • Patent number: 10381102
    Abstract: A semiconductor device is provided with normal memory cells constituted so as to store user data, reference memory cells constituted so as to generate a reference signal for reading out the normal memory cells, and a control circuit that carries out a defect detecting operation for detecting whether or not the reference memory cell and data stored in the reference memory cell are coincident with expected values on the stored data read out from the reference memory cells. Moreover, it is also provided with a control circuit for executing a defect correcting operation for correcting data to be stored in the reference memory cells that are detected as defective. Furthermore, it is also provided with a control circuit that is configured so as to cut off the reference memory cell detected as defective from the sense amplifier.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: August 13, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Kazuhiko Kajigaya
  • Patent number: 10381079
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. One method includes determining whether to access a first memory cell of a first memory cell array or a second memory cell of a second memory cell array, where a first digit line coupled to the first memory cell is coupled to a paging buffer register including a sense amplifier. The method further includes operating a transfer gate based at least in part on determining to read the second memory cell of the second memory cell array, where the transfer gate is configured to selectively couple a second digit line coupled to the second memory cell to the paging buffer register through the first digit line.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: August 13, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Kazuhiko Kajigaya
  • Publication number: 20190042120
    Abstract: Apparatuses and methods for controlling word lines and sense amplifiers in a semiconductor device are described.
    Type: Application
    Filed: August 4, 2017
    Publication date: February 7, 2019
    Applicant: Micron Technology, Inc.
    Inventor: Kazuhiko Kajigaya
  • Publication number: 20190035464
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. One method includes determining whether to access a first memory cell of a first memory cell array or a second memory cell of a second memory cell array, where a first digit line coupled to the first memory cell is coupled to a paging buffer register including a sense amplifier. The method further includes operating a transfer gate based at least in part on determining to read the second memory cell of the second memory cell array, where the transfer gate is configured to selectively couple a second digit line coupled to the second memory cell to the paging buffer register through the first digit line.
    Type: Application
    Filed: May 23, 2018
    Publication date: January 31, 2019
    Inventor: Kazuhiko Kajigaya
  • Publication number: 20190004713
    Abstract: Methods, systems, and devices for operating a memory device are described. One method includes caching data of a memory cell at a sense amplifier of a row buffer upon performing a first read of the memory cell; determining to perform at least a second read of the memory cell after performing the first read of the memory cell; and reading the data of the memory cell from the sense amplifier for at least the second read of the memory cell.
    Type: Application
    Filed: September 5, 2018
    Publication date: January 3, 2019
    Inventor: Kazuhiko Kajigaya
  • Patent number: 10082964
    Abstract: Methods, systems, and devices for operating a memory device are described. One method includes caching data of a memory cell at a sense amplifier of a row buffer upon performing a first read of the memory cell; determining to perform at least a second read of the memory cell after performing the first read of the memory cell; and reading the data of the memory cell from the sense amplifier for at least the second read of the memory cell.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: September 25, 2018
    Assignee: MICRON TECHNOLOGY, INC
    Inventor: Kazuhiko Kajigaya
  • Patent number: 10002666
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. One method includes determining whether to access a first memory cell of a first memory cell array or a second memory cell of a second memory cell array, where a first digit line coupled to the first memory cell is coupled to a paging buffer register including a sense amplifier. The method further includes operating a transfer gate based at least in part on determining to read the second memory cell of the second memory cell array, where the transfer gate is configured to selectively couple a second digit line coupled to the second memory cell to the paging buffer register through the first digit line.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: June 19, 2018
    Assignee: MICRON TECHNOLOGY, INC
    Inventor: Kazuhiko Kajigaya
  • Patent number: 9984739
    Abstract: Apparatuses and methods for controlling word lines and sense amplifiers in a semiconductor device are described. An example apparatus includes: a sub word line selection signal decoder which activates at least one of a plurality of sub word selection signals responsive to row address signals; a column segment selection signal decoder which activates at least one of a plurality of column segment signals responsive to a portion of column address signals and a portion of the row address signals; a column segment selection circuit which activates at least one of a plurality of column-subword selection signals responsive to the activated column segment signal and the activated sub word selection signal; and a sub word line driver which activates at least one of a plurality of sub word lines responsive to an activated main word line and the activated sub word selection signal.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: May 29, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Kazuhiko Kajigaya
  • Publication number: 20180122477
    Abstract: A device with error correction is provided. The device includes a plurality of memory cells, and reference read write circuit, a plurality of sense amplifiers, and an error-correction code control block. The reference read write circuit is configured to generate a reference voltage in response to data stored in at least one of the plurality of memory cells. A plurality of sense amplifiers are each coupled to a respective memory cell of the plurality of memory cells. An error-correction code (ECC) control block may output an error signal when the ECC control block detects that it is unable to correct error data in one or more respective memory cells. The reference read write circuit may overwrite data in the at least one of the plurality of memory cells in response to the error signal.
    Type: Application
    Filed: December 29, 2017
    Publication date: May 3, 2018
    Applicant: Micron Technology, Inc.
    Inventor: Kazuhiko Kajigaya
  • Patent number: 9892784
    Abstract: A device with error correction is provided. The device includes a plurality of memory cells, and reference read write circuit, a plurality of sense amplifiers, and an error-correction code control block. The reference read write circuit is configured to generate a reference voltage in response to data stored in at least one of the plurality of memory cells. A plurality of sense amplifiers are each coupled to a respective memory cell of the plurality of memory cells. An error-correction code (ECC) control block may output an error signal when the ECC control block detects that it is unable to correct error data in one or more respective memory cells. The reference read write circuit may overwrite data in the at least one of the plurality of memory cells in response to the error signal.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: February 13, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Kazuhiko Kajigaya