Abstract: An information processing apparatus includes a processor configured to set a state of a fixing device in a case where a state of an image forming apparatus including the fixing device transitions to a power saving state to be different depending on a property of the imaging forming apparatus.

Abstract: An information processing apparatus includes a processor configured to stepwisely change a power saving setting of an apparatus based on a usage status of the apparatus.

Abstract: An information processing apparatus includes a processor configured to output a set value of a transition time until an apparatus transitions to a power saving state, which is obtained based on a first history of a time interval of each processing executed by the apparatus and a target value of a return time required until the apparatus returns from the power saving state.

Abstract: An information processing apparatus includes a processor configured to change a power saving setting of an apparatus to a third setting in which a power saving effect is higher than in a second setting based on a usage status of the apparatus in a case where the power saving setting of the apparatus is changed from a first setting to the second setting; in which the first setting is a default setting of the apparatus, and the second setting is different from the third setting.

Abstract: According to one embodiment, a semiconductor storage device includes cells, and a sense amplifier. Each of the cells is connected to a bit line. The sense amplifier reads out data. The sense amplifier includes a first transistor to third transistor, and a switch. The first transistor has one end of a current path, the other end, and a gate. The second transistor has one end, and the other end. The second transistor has one of a first and a second supply ability. The third transistor has one end, and the other end. The third transistor has one of a third and a fourth supply ability. The switch grounds the second and the third transistors. The sense amplifier turns off the first transistor after transferring the data to an outside, and supplies the second signal to the switch to set gates of the second transistor and third transistor to ground.

Abstract: A method and apparatus for translating signals between different components located in different power boundaries in a mixed voltage system. A level shifter system includes a first level shifter circuit connected to a first voltage source. A second level shifter circuit connects to a second voltage source. An intermediate level shifter circuit has an input that connects to the output of the first level shifter circuit. The output of the intermediate level shifter circuit connects to the input of the second level shifter circuit. The intermediate level shifter circuit uses an intermediate voltage source having an intermediate voltage about midway between the first voltage of the first voltage source and the second voltage of the second voltage source.

Abstract: A reference current generating circuit includes an operational amplifier having one input terminal to receive a reference voltage and a field effect transistor having a gate to receive an output voltage of the operational amplifier. k resistors (k is an integer not less than 2) are connected in series to a drain of the field effect transistor, and a voltage at one of connection points of the resistors is feed backed to the other input terminal of the operational amplifier. A switch selects one of the connection points of the resistors and applies the voltage of the selected connection point as a reference voltage to a gate of a reference transistor to generate a reference current.

Abstract: According to one embodiment, a semiconductor storage device includes cells, and a sense amplifier. Each of the cells is connected to a bit line. The sense amplifier reads out data. The sense amplifier includes a first transistor to third transistor, and a switch. The first transistor has one end of a current path, the other end, and a gate. The second transistor has one end, and the other end. The second transistor has one of a first and a second supply ability. The third transistor has one end, and the other end. The third transistor has one of a third and a fourth supply ability. The switch grounds the second and the third transistors. The sense amplifier turns off the first transistor after transferring the data to an outside, and supplies the second signal to the switch to set gates of the second transistor and third transistor to ground.

Abstract: A method, an apparatus, and a computer program are provided to measure and/or correct duty cycles. Duty cycles of various signals, specifically clocking signals, are important. However, measurement of very high frequency signals, off-chip, and in a laboratory environment can be very difficult and present numerous problems. To combat problems associated with making off-chip measurements and adjustments of signal duty cycles, comparisons are made between input signals and divided input signals that allow for easy measurement and adjustment of on-chip signals, including clocking signals.

Abstract: A reference current generating circuit includes an operational amplifier having one input terminal to receive a reference voltage and a field effect transistor having a gate to receive an output voltage of the operational amplifier. k resistors (k is an integer not less than 2) are connected in series to a drain of the field effect transistor, and a voltage at one of connection points of the resistors is feed backed to the other input terminal of the operational amplifier. A switch selects one of the connection points of the resistors and applies the voltage of the selected connection point as a reference voltage to a gate of a reference transistor to generate a reference current.

Abstract: The present invention provides for a system comprising a level shifter configured to receive a first clock signal from a first power domain, to receive a counter signal, to select one of a plurality of intermediate voltages in response to the received counter signal, and to generate a second clock signal in response to the received first clock signal and the selected intermediate voltage. A counter is coupled to the level shifter and configured to receive a divided clock signal and a comparison result signal, and to generate the counter signal in response to the received divided clock signal and comparison result signal. A divider is coupled to the counter and configured to receive the first clock signal and to generate the divided clock signal in response to the received first clock signal. A filter is coupled to the level shifter and configured to receive the second clock signal and to generate a first comparison signal in response to the received second clock signal.

Abstract: A semiconductor integrated circuit device includes a processor, a first clock generating section and a control section. The processor core operates in synchronism with a first clock and includes first and second critical paths. The first clock generating section controls a duty of an externally input second clock to generate the first clock. a control section detects a first phase difference between the first clock and a third clock obtained by delaying the first clock by a delay time in the first critical path and a second phase difference between the first clock and a fourth clock obtained by delaying the first clock by a delay time in the second critical path. The control section instructs the first clock generating section to control the duty so as to minimize a difference between the first and second phase differences.

Abstract: A technology for supplying a power supply voltage to a microprocessor. Before normal arithmetic processing of the microprocessor, duty cycle correction process for adjusting the duty cycle of a clock signal inside the microprocessor is performed. In the duty cycle correction process for adjusting the duty cycle, the duty cycle of the clock signal is adjusted so as to minimize the power voltage at which the microprocessor is still operable.

Abstract: A semiconductor memory device comprises a sense amplifier circuit having a first and a second input terminal, the sense amplifier configured to compare current flowing in the first input terminal with current flowing in the second input terminal, and the sense amplifier configured to provide the result to external; a first gate circuit connected to the first input terminal, the first gate circuit configured to pass a cell current flowing in a memory cell to the first input terminal; a reference current source, the reference current source configured to feed a reference current to the second input terminal, the reference current serving as the reference for level sensing the cell current; a second gate circuit connected to the second input terminal, the second gate circuit including a replica circuit of the first gate circuit; a first current source configured to feed a first current to the first input terminal, the first current corresponding to the offset at the time of read from a first-state cell; and a se

Abstract: The present invention provides a method, an apparatus, and a computer program product for measuring the temperature of a microprocessor through the use of ESD circuitry. The present invention uses diodes and an I/O pad within ESD circuits to determine the temperature at the location of the ESD circuitry. First, a current measuring device connects to a diode. A user or a computer program disables the protected component or circuitry, and subsequently applies a predetermined voltage to the I/O pad. This creates a reverse saturation current through the diode, which is measured by the current measuring device. From this current the user or a computer program determines the temperature of the microprocessor at the diode through the use of a graphical representation of diode reverse saturation current and corresponding temperature.

Abstract: A semiconductor integrated circuit device includes a processor, a first clock generating section and a control section. The processor core operates in synchronism with a first clock and includes first and second critical paths. The first clock generating section controls a duty of an externally input second clock to generate the first clock. a control section detects a first phase difference between the first clock and a third clock obtained by delaying the first clock by a delay time in the first critical path and a second phase difference between the first clock and a fourth clock obtained by delaying the first clock by a delay time in the second critical path. The control section instructs the first clock generating section to control the duty so as to minimize a difference between the first and second phase differences.

Abstract: The present invention provides for a system comprising a level shifter configured to receive a first clock signal from a first power domain, to receive a counter signal, to select one of a plurality of intermediate voltages in response to the received counter signal, and to generate a second clock signal in response to the received first clock signal and the selected intermediate voltage. A counter is coupled to the level shifter and configured to receive a divided clock signal and a comparison result signal, and to generate the counter signal in response to the received divided clock signal and comparison result signal. A divider is coupled to the counter and configured to receive the first clock signal and to generate the divided clock signal in response to the received first clock signal. A filter is coupled to the level shifter and configured to receive the second clock signal and to generate a first comparison signal in response to the received second clock signal.

Abstract: The present invention provides for a system comprising a level shifter configured to receive a first clock signal from a first power domain, to receive a counter signal, to select one of a plurality of intermediate voltages in response to the received counter signal, and to generate a second clock signal in response to the received first clock signal and the selected intermediate voltage. A counter is coupled to the level shifter and configured to receive a divided clock signal and a comparison result signal, and to generate the counter signal in response to the received divided clock signal and comparison result signal. A divider is coupled to the counter and configured to receive the first clock signal and to generate the divided clock signal in response to the received first clock signal. A filter is coupled to the level shifter and configured to receive the second clock signal and to generate a first comparison signal in response to the received second clock signal.

Abstract: A method, an apparatus, and a computer program are provided to measure and/or correct duty cycles. Duty cycles of various signals, specifically clocking signals, are important. However, measurement of very high frequency signals, off-chip, and in a laboratory environment can be very difficult and present numerous problems. To combat problems associated with making off-chip measurements and adjustments of signal duty cycles, comparisons are made between input signals and divided input signals that allow for easy measurement and adjustment of on-chip signals, including clocking signals.

Abstract: A method, an apparatus, and a computer program are provided to measure and/or correct duty cycles. Duty cycles of various signals, specifically clocking signals, are important. However, measurement of very high frequency signals, off-chip, and in a laboratory environment can be very difficult and present numerous problems. To combat problems associated with making off-chip measurements and adjustments of signal duty cycles, comparisons are made between input signals and divided input signals that allow for easy measurement and adjustment of on-chip signals, including clocking signals.