Abstract: A method and an apparatus for testing a phase-locked loop (PLL) are provided. A fixed-level reference clock signal and a test feedback clock signal are applied to a phase-frequency detector (PFD) of the PLL to measure a minimum output frequency of a voltage-controlled oscillator (VCO) of the PLL. A test reference clock signal and a fixed-level feedback clock signal are applied to the PFD to measure a maximum output frequency of the VCO. The lock and capture range of the PLL is determined based on the maximum and minimum frequencies of the VCO.

Abstract: A nonvolatile semiconductor memory of this invention includes a data storage read cell in which the threshold is set to turn on/off the read cell in accordance with storage data upon selection, a reference cell in which the threshold is set to turn on the reference cell upon selection, and a flip-flop type amplifier for reading out whether the read cell is an ON or OFF cell. In this nonvolatile semiconductor memory, whether the read cell is an ON or OFF cell is read out by comparing changes in bit line voltages of the read and reference cells using the flip-flop type sense amplifier by a method of performing precharge and then discharge. At this time, a word line connected to the read cell is set to a selected state in synchronism with the start of precharge, and a word line connected to the reference cell is set to a selected state in synchronism with the end of precharge.

Abstract: A non-volatile semiconductor memory device raises the word line voltage by use of the edge of a clock to read out memory cell data. A plurality of voltage raising circuits are connected in parallel and each of the voltage raising circuits raises a power supply voltage. A level shifter is connected to the outputs of the plurality of voltage raising circuits to drive the word line. Driving means drives each of the plurality of voltage raising circuits by use of clocks each having only one edge in a period from the address changing time to the memory cell data readout starting time at which the precharging operation is terminated. The clocks for driving the voltage raising circuits have a phase difference with respect to one another for the respective voltage raising circuits.

Abstract: The present invention relates to a precharge/discharge nonvolatile memory circuit for detecting signals output from two bit lines on read-cell and dummy cell sides using a flip-flop circuit, comprising a first row decoder on the read-cell side, a second row decoder on the dummy-cell side, a first column decoder on the read-cell side, a second column decoder on the dummy-cell side, a read cell selected by the first row decoder and the first column decoder, a dummy cell selected by the second row decoder and the second column decoder, first and second precharge transistors for performing a precharge operation, first and second discharge transistors for performing a discharge operation, the flip-flop circuit, a discharge control circuit for generating a discharge signal, and a precharge control circuit for generating a precharge signal after the discharge signal is generated from the discharge control circuit.