Abstract: An apparatus, a method, and a computer program are provided to measure the duty cycle of a clocking signal in a processor. Traditionally, variations in the duty cycles of clocks within microprocessors have been of considerable concern. By employing frequency dividers and AND gates, the duty cycles of clocks can be precisely measured and adjusted accordingly to account for variation that might occur. The measurements and adjustments, therefore, can improve the operation of a microprocessor or any other clocked semiconductor.

Abstract: A level shifter apparatus and method for minimizing duty cycle distortion are provided. The level shifter includes a bank of comparators each having an associated threshold built into it. The comparators compare a difference in source voltages for two power domains to these built-in thresholds and output a signal indicative of whether the threshold is exceeded. The output signals from the comparators are provided to a thermometric decoder which generates control signals based on these output signals. The control signals are used to control stages in a level shifter for modifying the voltage output of the level shifter. Individual stages may be enabled to thereby monotonically modify the voltage output of the level shifter and thereby decrease a time required to achieve a voltage having a level that causes a state change in a driven circuit. As a result, duty cycle distortion is minimized and maximum operational frequency is increased.

Abstract: A system and method for configuring a phased-lock loop (PLL) dividing ratio which does not require the phased-lock loop circuit to lock. In one embodiment, the method includes inducing a substantially minimum or a substantially maximum frequency output from a voltage-controlled oscillator (VCO), and configuring a divider with a corresponding dividing ratio. The method may include grounding an input voltage to the VCO. Alternately, the method may include manipulating inputs to a charge pump providing input to the VCO. The charge pump inputs may be manipulated directly or through a phase-frequency detector providing input to the charge pump and adapted to receive additional input signals.

Abstract: The present invention provides for a system comprising a first stable voltage module configured to receive a first power supply from a first power supply domain and to generate a first stable voltage in response to the received first power supply. A second stable voltage module is configured to receive a second power supply from a second power supply domain and to generate a second stable voltage in response to the received second power supply. A first set of resistors is coupled to the first stable voltage module and configured in parallel. A second set of resistors is coupled to the second stable voltage module and configured in parallel. A set of capacitors is coupled in parallel to the first set of resistors and the second set of resistors and a plurality of level shifters are coupled to the second set of resistors.

Abstract: The present invention provides a method, an apparatus, and a computer program product for measuring the temperature of a microprocessor through the use of ESD circuitry. The present invention uses diodes and an I/O pad within ESD circuits to determine the temperature at the location of the ESD circuitry. First, a current measuring device connects to a diode. A user or a computer program disables the protected component or circuitry, and subsequently applies a predetermined voltage to the I/O pad. This creates a reverse saturation current through the diode, which is measured by the current measuring device. From this current the user or a computer program determines the temperature of the microprocessor at the diode through the use of a graphical representation of diode reverse saturation current and corresponding temperature.

Abstract: The present invention provides for compensation of leakage charge in a PLL. A first plurality and second plurality of charge pumps has a source charge pump and a sink charge pump, and each charge pump has its own switch. A first node is coupled between at least one source charge pump and at least one sink charge pump. A second node coupled between at least one source charge pump and at least one sink charge pump. A PLL filter is coupled to the first node. A dummy filter is coupled to the second node. A first input of a differential mode sensor is coupled to the PLL filter. A second input of a differential mode sensor is coupled to the dummy filter. A first input of a common mode sensor is coupled to the dummy filter. A second input of a common mode sensor coupled to the PLL filter.

Abstract: The present invention provides a method, apparatus, and computer program for measuring the current leakage in a Low Pass Filter (LPF) capacitor of a Phased Locked Loop (PLL). As a result of thinner and thinner film capacitors in Complementary Metal-Oxide Semiconductor (CMOS) technology, leakage current, which causes a PLL to drift out of phase lock, has become an increasingly difficult problem. To overcome the leakage current problems, knowing the leakage current of an LPF capacitor is important to implement the correction circuitry. In the present invention, an external interface and a time interface analyzer are used to charge the LPF capacitor and measure the output frequency of the PLL's Voltage Controlled Oscillator. Because of the change in the output frequency, the leakage current can be determined.

Abstract: A method and apparatus for translating signals between different components located in different power boundaries in a mixed voltage system. A level shifter system includes a first level shifter circuit connected to a first voltage source. A second level shifter circuit connects to a second voltage source. An intermediate level shifter circuit has an input that connects to the output of the first level shifter circuit. The output of the intermediate level shifter circuit connects to the input of the second level shifter circuit. The intermediate level shifter circuit uses an intermediate voltage source having an intermediate voltage about midway between the first voltage of the first voltage source and the second voltage of the second voltage source.

Abstract: The present invention provides for a system comprising a level shifter configured to receive a first clock signal from a first power domain, to receive a counter signal, to select one of a plurality of intermediate voltages in response to the received counter signal, and to generate a second clock signal in response to the received first clock signal and the selected intermediate voltage. A counter is coupled to the level shifter and configured to receive a divided clock signal and a comparison result signal, and to generate the counter signal in response to the received divided clock signal and comparison result signal. A divider is coupled to the counter and configured to receive the first clock signal and to generate the divided clock signal in response to the received first clock signal. A filter is coupled to the level shifter and configured to receive the second clock signal and to generate a first comparison signal in response to the received second clock signal.

Abstract: Devices, methods, and systems for initializing a phased-lock loop (PLL) circuit which prevents or reduces the occurrences of voltage-controlled oscillator (VCO) frequency exceeding a divider's maximum input frequency, thus preventing or reducing at least one cause of lock failure. Disclosed is a PLL circuit having logic circuitry configured to hold a PFD reference-signal input low and provide a divided reference-signal to a PFD feedback-signal input while an initialization signal is asserted. The PLL can be initialized without adding circuitry to a VCO input. By asserting an initialization signal, an input voltage to a voltage-controlled oscillator is attenuated. The initialization signal is adapted to gate inputs to and outputs from the phase-locked loop circuit.

Abstract: A system and method for configuring a phased-lock loop (PLL) dividing ratio which does not require the phased-lock loop circuit to lock. In one embodiment, the method includes inducing a substantially minimum or a substantially maximum frequency output from a voltage-controlled oscillator (VCO), and configuring a divider with a corresponding dividing ratio. The method may include grounding an input voltage to the VCO. Alternately, the method may include manipulating inputs to a charge pump providing input to the VCO. The charge pump inputs may be manipulated directly or through a phase-frequency detector providing input to the charge pump and adapted to receive additional input signals.

Abstract: A method, an apparatus, and a computer program are provided to measure and/or correct duty cycles. Duty cycles of various signals, specifically clocking signals, are important. However, measurement of very high frequency signals, off-chip, and in a laboratory environment can be very difficult and present numerous problems. To combat problems associated with making off-chip measurements and adjustments of signal duty cycles, comparisons are made between input signals and divided input signals that allow for easy measurement and adjustment of on-chip signals, including clocking signals.

Abstract: A method and an apparatus for testing a phase-locked loop (PLL) are provided. A fixed-level reference clock signal and a test feedback clock signal are applied to a phase-frequency detector (PFD) of the PLL to measure a minimum output frequency of a voltage-controlled oscillator (VCO) of the PLL. A test reference clock signal and a fixed-level feedback clock signal are applied to the PFD to measure a maximum output frequency of the VCO. The lock and capture range of the PLL is determined based on the maximum and minimum frequencies of the VCO.

Abstract: An apparatus, a method, and a computer program are provided to measure the duty cycle of a clocking signal in a processor. Traditionally, variations in the duty cycles of clocks within microprocessors have been of considerable concern. By employing frequency dividers and AND gates, the duty cycles of clocks can be precisely measured and adjusted accordingly to account for variation that might occur. The measurements and adjustments, therefore, can improve the operation of a microprocessor or any other clocked semiconductor.

Abstract: Systems and methods for measuring the characteristics of voltage controlled oscillators within these circuits and initializing the circuits without coupling circuitry to the voltage control node that could introduce noise at this node. One embodiment includes a PLL circuit having a charge pump and control circuitry for driving the charge pump, where the control circuitry is configured to provide “up” and “down” signals to the charge pump in a normal operational mode or a test/initialization mode. In the normal mode, the control circuitry passes signals received from a phase frequency detector through to the charge pump as the up and down signals. In the test/initialization mode, the control circuitry overrides at least one of the signals received from the phase frequency detector to drive the charge pump to generate a selectable test voltage which is used by a voltage controlled oscillator to generate an output signal at a corresponding frequency.

Abstract: The present invention provides for compensation of leakage charge in a PLL. A first plurality and second plurality of charge pumps has a source charge pump and a sink charge pump, and each charge pump has its own switch. A first node is coupled between at least one source charge pump and at least one sink charge pump. A second node coupled between at least one source charge pump and at least one sink charge pump. A PLL filter is coupled to the first node. A dummy filter is coupled to the second node. A first input of a differential mode sensor is coupled to the PLL filter. A second input of a differential mode sensor is coupled to the dummy filter. A first input of a common mode sensor is coupled to the dummy filter. A second input of a common mode sensor coupled to the PLL filter.

Abstract: Systems and methods for measuring the characteristics of voltage controlled oscillators within these circuits and initializing the circuits without coupling circuitry to the voltage control node that could introduce noise at this node. One embodiment comprises a PLL circuit having a charge pump and control circuitry for driving the charge pump, where the control circuitry is configured to provide “up” and “down” signals to the charge pump in a normal operational mode or a test/initialization mode. In the normal mode, the control circuitry passes signals received from a phase frequency detector through to the charge pump as the up and down signals. In the test/initialization mode, the control circuitry overrides at least one of the signals received from the phase frequency detector to drive the charge pump to generate a selectable test voltage which is used by a voltage controlled oscillator to generate an output signal at a corresponding frequency.

Abstract: The present invention provides a method, apparatus, and computer program for measuring the current leakage in a Low Pass Filter (LPF) capacitor of a Phased Locked Loop (PLL). As a result of thinner and thinner film capacitors in Complementary Metal-Oxide Semiconductor (CMOS) technology, leakage current, which causes a PLL to drift out of phase lock, has become an increasingly difficult problem. To overcome the leakage current problems, knowing the leakage current of an LPF capacitor is important to implement the correction circuitry. In the present invention, an external interface and a time interface analyzer are used to charge the LPF capacitor and measure the output frequency of the PLL's Voltage Controlled Oscillator. Because of the change in the output frequency, the leakage current can be determined.

Abstract: Lock detectors are provided that have a narrow sensitivity range.

Abstract: Lock detectors are provided that have a narrow sensitivity range.