Patents by Inventor Kazuhiro Adachi

Kazuhiro Adachi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7657778
    Abstract: When a primary computer is taken over to a secondary computer in a redundancy configuration computer system where booting is performed via a storage area network (SAN), a management server delivers an information collection/setting program to the secondary computer before the user's operating system of the secondary computer is started. This program assigns a unique ID (World Wide Name), assigned to the fibre channel port of the primary computer, to the fibre channel port of the secondary computer to allow a software image to be taken over from the primary computer to the secondary computer.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: February 2, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Tetsuhiro Goto, Kazuhiro Adachi
  • Publication number: 20070073875
    Abstract: When a primary computer is taken over to a secondary computer in a redundancy configuration computer system where booting is performed via a storage area network (SAN), a management server delivers an information collection/setting program to the secondary computer before the user's operating system of the secondary computer is started. This program assigns a unique ID (World Wide Name), assigned to the fibre channel port of the primary computer, to the fibre channel port of the secondary computer to allow a software image to be taken over from the primary computer to the secondary computer.
    Type: Application
    Filed: September 19, 2006
    Publication date: March 29, 2007
    Inventors: Tetsuhiro Goto, Kazuhiro Adachi
  • Publication number: 20060057796
    Abstract: A silicon carbide vertical MOSFET having low ON-resistance and high blocking voltage. A first deposition film of low concentration silicon carbide of a first conductivity type is formed on the surface of a high concentration silicon carbide substrate of a first conductivity type. Formed on the first deposition film is a second deposition film that includes a high concentration gate region of a second conductivity type, with a first region removed selectively. A third deposition film is formed on the second deposition film, which includes a second region that is wider than the selectively removed first region, a high concentration source region of a first conductivity type, and a low concentration gate region of a second conductivity type. A low concentration base region of a first conductivity type is formed in contact with the first deposition film in the first and second regions.
    Type: Application
    Filed: October 3, 2003
    Publication date: March 16, 2006
    Inventors: Shinsuke Harada, Tsutomu Yatsuo, Kenji Fukuda, Mitsuo Okamoto, Kazuhiro Adachi
  • Patent number: 6850963
    Abstract: An information service providing method for providing an information service is provided, wherein the method includes the steps of: receiving a customer's request for the information service to be provided with; deciding the customer's utilization qualification with respect to the contents of the information service; determining the contents that is available to the customer according to the customer's utilization qualification among the contents of the information service that the customer requests to be provided with; and providing the customer with the determined contents of the information service.
    Type: Grant
    Filed: September 5, 2000
    Date of Patent: February 1, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhiro Adachi, Masahiro Akahori, Katsuhisa Fukuda, Takahiro Yoshida
  • Patent number: 6812102
    Abstract: In a semiconductor device using a silicon carbide substrate (1), the object of the present invention is to provide a method of manufacturing a semiconductor device that is a buried channel region type transistor having hot-carrier resistance, high punch-through resistance and high channel mobility. This is achieved by using a method of manufacturing a buried channel type transistor using a P-type silicon carbide substrate that includes a step of forming a buried channel region, a source region and a drain region, a step of forming a gate insulation layer after the step of forming the buried channel region, source region and drain region, and a step of exposing the gate insulation layer to an atmosphere containing water vapor at a temperature of 500° C. or more after the step of forming the gate insulation layer. The gate insulation layer is formed by a thermal oxidation method using dry oxygen.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: November 2, 2004
    Assignees: National Institute of Advanced Industrial Science and Technology, Japan Science and Technology Corporation, Sanyo Electric Co., Ltd.
    Inventors: Kenji Fukuda, Kazuo Arai, Junji Senzaki, Shinsuke Harada, Ryoji Kosugi, Kazuhiro Adachi, Seiji Suzuki
  • Patent number: 6759684
    Abstract: An MIS transistor that uses a silicon carbide substrate has a buried channel structure. The surface orientation of the silicon carbide substrate is optimized so that the device does not assume a normally on state, has good hot-carrier endurance and punch-through endurance, and high channel mobility. In particular, a P-type silicon carbide semiconductor substrate is used to form a buried channel region. To achieve high mobility, the depth at which the buried channel region is formed is optimized, and the ratio between buried channel region junction depth (Lbc) source and drain region junction depth (Xj) is made to be within 0.2 to 1.0. The device can be formed on any surface of a hexagonal or rhombohedral or a (110) surface of a cubic system silicon carbide crystal, and provides a particularly good effect when formed on the (11-20) surface.
    Type: Grant
    Filed: November 14, 2001
    Date of Patent: July 6, 2004
    Assignees: National Institute of Advanced Industrial Science and Technology, Japan Science and Technology Corporation
    Inventors: Kenji Fukuda, Kazuo Arai, Junji Senzaki, Shinsuke Harada, Ryoji Kosugi, Kazuhiro Adachi
  • Publication number: 20040087093
    Abstract: In a semiconductor device using a silicon carbide substrate (1), the object of the present invention is to provide a method of manufacturing a semiconductor device that is a buried channel region type transistor having hot-carrier resistance, high punch-through resistance and high channel mobility. This is achieved by using a method of manufacturing a buried channel type transistor using a P-type silicon carbide substrate that includes a step of forming a buried channel region, a source region and a drain region, a step of forming a gate insulation layer after the step of forming the buried channel region, source region and drain region, and a step of exposing the gate insulation layer to an atmosphere containing water vapor at a temperature of 500° C. or more after the step of forming the gate insulation layer. The gate insulation layer is formed by a thermal oxidation method using dry oxygen.
    Type: Application
    Filed: December 30, 2003
    Publication date: May 6, 2004
    Inventors: Kenji Fukuda, Kazuo Arai, Junji Senzaki, Shinsuke Harada, Ryoji Kosugi, Kazuhiro Adachi, Seiji Suzuki
  • Publication number: 20020111004
    Abstract: In a semiconductor device having a fuse and an etching stopper film covering the fuse, an optical window exposing the etching stopper film and a contact hole exposing a conductor pattern are formed simultaneously. By applying a dry etching process further to the etching stopper film, an insulation film covering the fuse is exposed in the optical window.
    Type: Application
    Filed: April 18, 2002
    Publication date: August 15, 2002
    Applicant: FUJITSU LIMITED
    Inventors: Seiichi Suzuki, Kazuhiro Adachi, Masaya Katayama, Noriyuki Suzuki, Osamu Hideshima, Kenichi Kawabata, Masaya Ohtsuki, Manabu Hayashi, Junichi Yayanagi
  • Patent number: 6399472
    Abstract: In a semiconductor device having a fuse and an etching stopper film covering the fuse, an optical window exposing the etching stopper film and a contact hole exposing a conductor pattern are formed simultaneously. By applying a dry etching process further to the etching stopper film, an insulation film covering the fuse is exposed in the optical window.
    Type: Grant
    Filed: June 11, 1999
    Date of Patent: June 4, 2002
    Assignee: Fujitsu Limited
    Inventors: Seiichi Suzuki, Kazuhiro Adachi, Masaya Katayama, Noriyuki Suzuki, Osamu Hideshima, Kenichi Kawabata, Masaya Ohtsuki, Manabu Hayashi, Junichi Yayanagi
  • Publication number: 20020047125
    Abstract: An MIS transistor that uses a silicon carbide substrate has a buried channel structure. The surface orientation of the silicon carbide substrate is optimized so that the device does not assume a normally on state, has good hot-carrier endurance and punch-through endurance, and high channel mobility. In particular, a P-type silicon carbide semiconductor substrate is used to form a buried channel region. To achieve high mobility, the depth at which the buried channel region is formed is optimized, and the ratio between buried channel region junction depth (Lbc) source and drain region junction depth (Xj) is made to be within 0.2 to 1.0. The device can be formed on any surface of a hexagonal or rhombohedral or a (110) surface of a cubic system silicon carbide crystal, and provides a particularly good effect when formed on the (11-20) surface.
    Type: Application
    Filed: November 14, 2001
    Publication date: April 25, 2002
    Applicant: Nat ' l Inst. of Advanced industrial and Technology
    Inventors: Kenji Fukuda, Kazuo Arai, Junji Senzaki, Shinsuke Harada, Ryoji Kosugi, Kazuhiro Adachi
  • Publication number: 20010049814
    Abstract: The problem of the disclosed technique is to realize an automatic logic design supporting method and apparatus capable of laying out a circuit of logic synthesis result so as to be able to satisfy delay constraints without changing the logic structure.
    Type: Application
    Filed: March 20, 2001
    Publication date: December 6, 2001
    Inventors: Kazuhiko Matsumoto, Kazuhiro Adachi, Tomoko Ishida