Abstract: A semiconductor storage device includes a substrate and a memory cell array. The memory cell array is above the substrate in a first direction. The memory cell array includes first to third regions arranged in a second direction. The memory cell array comprises a first stack in the first and third regions, first and second semiconductor layers extending through the first stack in the first and third regions, respectively, a second stack in the second region, a first contact extending through the second stack, a fourth insulating layer extending in the first and second directions in the second region, and a fifth insulating layer extending in the first direction and a third direction in the second region. A distance from a bottom end of the fourth insulating layer to the substrate is different from a distance from a bottom end of the fifth insulating layer to the substrate.

Abstract: According to one embodiment, a misalignment measuring apparatus includes: an input circuit; a storage medium; a first circuit configured to, in a first calibration pattern, calculate a second misalignment amount; a second circuit configured to, using a first image of a second calibration pattern, calculate a third misalignment amount; a third circuit configured to calculate a coefficient indicating; and a fourth circuit configured to, using a second image corresponding to the first and second patterns, calculate a third center position of a third contour and calculate the first misalignment amount between the first pattern and the second pattern based on the fourth misalignment amount and the coefficient.

Abstract: According to one embodiment, a device includes a memory cell array that includes a plurality of memory cells connected to a plurality of pieces of gate wiring, and a test control circuit that includes a plurality of control units connected to the plurality of pieces of gate wiring. The control units each includes a transistor that includes a gate connected to a first node, one end connected to the corresponding gate wiring and another end connected to a second node, and a load unit connected between the first node and the second node. When the gate wiring is being discharged, the transistor is turned on. The gate wiring is connected to the second node via the transistor in an on state. After the gate wiring is discharged, the load unit discharges the first node.

Abstract: A semiconductor storage device according to an embodiment includes a board, an electronic component, and a holder. The board has a first surface. The electronic component includes a component main body and a first lead. The component main body is at a position out of the board in a direction parallel to the first surface. The first lead protrudes from the component main body toward the board. The holder is on the board. The holder holds the first lead.

Abstract: A semiconductor memory device according to an embodiment includes a base, a first conductor, a second conductor, a first pillar, a first insulating member, and a first contact. The first conductor is provided in a first layer above the base. The second conductor is provided above the first conductor. The first pillar includes a first portion and a second portion formed by different bodies. The first portion of the first pillar is provided to penetrate the first conductor. The second portion of the first pillar is provided to penetrate the second conductor. The first insulating member is provided at least in the first layer. The first contact is contacting the second conductor above the first insulating member.

Abstract: A semiconductor storage device includes a logic circuit formed on a substrate, a first area formed on the logic circuit and has a plurality of first insulating layers and a plurality of conductive layers alternately stacked in a first direction, a plurality of memory pillars MP which extend in the first area in the first direction, a second area which is formed on the logic circuit and has the plurality of first insulating layers 33 and a plurality of second insulating layers alternately stacked in the first direction, and a contact plug CP1 which extends in the second area in the first direction and is connected to the logic circuit.

Abstract: In one embodiment, a semiconductor device includes a substrate, a lower pad provided above the substrate, and an upper pad provided on the lower pad. The lower pad includes a first pad and a plurality of first connection portions provided on the first pad, and the upper pad is provided on the plurality of first connection portions, or the upper pad includes a second pad and a plurality of second connection portions provided under the second pad, and the lower pad is provided under the plurality of second connection portions.

Abstract: In one embodiment, a semiconductor device includes a first insulator, a plurality of interconnections provided in the first insulator. The device further includes a second insulator provided on the first insulator and the plurality of interconnections, and a conductor provided on a first interconnection among the plurality of interconnections and having a shape that is projected upwardly with respect to the first interconnection in the second insulator. The device further includes a plug provided on the first interconnection via the conductor. The device further includes a first pad provided above the plug and electrically connected to the plug, and a second pad provided on the first pad and electrically connected to the first pad.

Abstract: Semiconductor memory device includes: a first and second member each extending in a first direction in a boundary part between a first and second block region and arranged in the first direction; a support pillar arranged between the first and second member at the boundary part; conductive layers separated from one another and arranged in a third direction and split by the first and second member, and the support pillar into a first and second portion; and a memory pillar penetrating through the conductive layers. The support pillar includes a lower and upper pillar. A side face of the lower pillar and an extension of a side face of the upper pillar are displaced from each other in a plane based on a second and the third direction.

Abstract: According to one embodiment, a semiconductor storage device includes a stacked section in which a plurality of conductor layers are stacked along a first direction and a stepped section in which the plurality of conductor layers are in a stepped shape. The stepped section includes a lower stepped section and an upper stepped section. In the upper stepped section, the conductor layers closer to the lower stepped section side along the first direction extend longer toward one side along a second direction orthogonal to the first direction. The lower stepped section is located at a position toward an opposite side to the one side along the second direction with respect to the upper stepped section.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked layer body including conductive and insulating layers alternately stacked in a first direction, partition structures each extending in first and second directions in the stacked layer body, and an intermediate structure extending from an upper end and terminating at a position between upper and lower ends of the stacked layer body between adjacent partition structures. The partition structures include a first partition structure including first and second portions arranged in the second direction, the first portion extends from the upper end to the lower end, and the second portion is located between adjacent first portions, extends from the upper end and terminates at the position between the upper and lower ends.

Abstract: A semiconductor storage device includes a substrate and a memory cell array. The memory cell array is above the substrate in a first direction. The memory cell array includes first to third regions arranged in a second direction. The memory cell array comprises a first stack in the first and third regions, first and second semiconductor layers extending through the first stack in the first and third regions, respectively, a second stack in the second region, a first contact extending through the second stack, a fourth insulating layer extending in the first and second directions in the second region, and a fifth insulating layer extending in the first direction and a third direction in the second region. A distance from a bottom end of the fourth insulating layer to the substrate is different from a distance from a bottom end of the fifth insulating layer to the substrate.

Abstract: A semiconductor memory device according to an embodiment includes a substrate. The substrate includes first and second areas, and block areas. The second area includes subareas. Each of the subareas includes a contact area and an insulating area arranged in the first direction. The contact area includes terraced portions and first contacts corresponding to two block areas. The insulating area includes second contacts corresponding to the two block areas. Contact areas of odd-numbered subareas and insulating areas of even-numbered subareas are disposed in an alternating manner in the second direction. Insulating areas of the odd-numbered subareas and contact areas of the even-numbered subareas are disposed in an alternating manner in the second direction.

Abstract: According to one embodiment, a misalignment measuring apparatus includes: an input circuit; a storage medium; a first circuit configured to, in a first calibration pattern, calculate a second misalignment amount; a second circuit configured to, using a first image of a second calibration pattern, calculate a third misalignment amount; a third circuit configured to calculate a coefficient indicating; and a fourth circuit configured to, using a second image corresponding to the first and second patterns, calculate a third center position of a third contour and calculate the first misalignment amount between the first pattern and the second pattern based on the fourth misalignment amount and the coefficient.

Abstract: According to one embodiment, a semiconductor memory device includes: a plurality of first interconnect layers including first and second conductors; a second interconnect layer arranged above the first interconnect layers; a third interconnect layer arranged adjacently to the second interconnect layer; a first pillar passing through the first interconnect layers and the second interconnect layer; a second pillar passing through the first interconnect layers and the third interconnect layer; and a third pillar arranged between the second interconnect layer and the third interconnect layer and passing through the first interconnect layers. The second conductor covers a top surface and a bottom surface of the first conductor, and a side surface of an end portion of the first conductor.

Abstract: A semiconductor storage device includes a logic circuit formed on a substrate, a first area formed on the logic circuit and has a plurality of first insulating layers and a plurality of conductive layers alternately stacked in a first direction, a plurality of memory pillars MP which extend in the first area in the first direction, a second area which is formed on the logic circuit and has the plurality of first insulating layers 33 and a plurality of second insulating layers alternately stacked in the first direction, and a contact plug CP1 which extends in the second area in the first direction and is connected to the logic circuit.

Abstract: A a semiconductor storage device includes a logic circuit formed on a substrate, a first area formed on the logic circuit and has a plurality of first insulating layers and a plurality of conductive layers alternatively stacked in a first direction, a plurality of memory pillars MP which extend in the first area in the first direction, a second area which is formed on the logic circuit and has the plurality of first insulating layers 33 and a plurality of second insulating layers alternately stacked in the first direction, and a contact ping CP1 which extends in the second area in the first direction and is connected to the logic circuit.

Abstract: In one embodiment, a semiconductor device includes a first insulator, a plurality of interconnections provided in the first insulator. The device further includes a second insulator provided on the first insulator and the plurality of interconnections, and a conductor provided on a first interconnection among the plurality of interconnections and having a shape that is projected upwardly with respect to the first interconnection in the second insulator. The device further includes a plug provided on the first interconnection via the conductor. The device further includes a first pad provided above the plug and electrically connected to the plug, and a second pad provided on the first pad and electrically connected to the first pad.

Abstract: A semiconductor memory device according to an embodiment includes a base, a first conductor, a second conductor, a first pillar, a first insulating member, and a first contact. The first conductor is provided in a first layer above the base. The second conductor is provided above the first conductor. The first pillar includes a first portion and a second portion formed by different bodies. The first portion of the first pillar is provided to penetrate the first conductor. The second portion of the first pillar is provided to penetrate the second conductor. The first insulating member is provided at least in the first layer. The first contact is contacting the second conductor above the first insulating member.

Abstract: An apparatus for inspecting a defect includes a memory storage and a processing unit coupled to the memory storage. The processing unit is configured to acquire pattern data for one or more patterns implemented on a wafer from a storage device, clip a portion that corresponds to the pattern data from a figure indicated by design data to generate design information and one or more circuit patterns, assign a first set of numbers to the one or more patterns of the pattern data, assign a second set of numbers to the one or more circuit patterns of the design information, generate relation information indicative of one or more correspondences between the first set of numbers and the second set of numbers, verify whether or not the one or more patterns indicated by the pattern data constitute a crucial defect based on the relation information, and send a verification result to a device.