Abstract: According to one embodiment, a semiconductor memory device includes: a plurality of first interconnect layers including first and second conductors; a second interconnect layer arranged above the first interconnect layers; a third interconnect layer arranged adjacently to the second interconnect layer; a first pillar passing through the first interconnect layers and the second interconnect layer; a second pillar passing through the first interconnect layers and the third interconnect layer; and a third pillar arranged between the second interconnect layer and the third interconnect layer and passing through the first interconnect layers. The second conductor covers a top surface and a bottom surface of the first conductor, and a side surface of an end portion of the first conductor.

Abstract: In one embodiment, a semiconductor device includes a substrate, a lower pad provided above the substrate, and an upper pad provided on the lower pad. The lower pad includes a first pad and a plurality of first connection portions provided on the first pad, and the upper pad is provided on the plurality of first connection portions, or the upper pad includes a second pad and a plurality of second connection portions provided under the second pad, and the lower pad is provided under the plurality of second connection portions.

Abstract: According to one embodiment, there is provided a memory device which includes a plurality of elements that include three-dimensionally arranged memory cells, a transistor that is electrically connected to at least one of the plurality of elements, an inspection pad that is connected in series to at least one of the plurality of elements through the transistor, and a wiring that is electrically connected to the inspection pad and a gate of the transistor and capable of supplying a common potential to both the inspection pad and the transistor for turning the transistor to an OFF state.

Abstract: A a semiconductor storage device includes a logic circuit formed on a substrate, a first area formed on the logic circuit and has a plurality of first insulating layers and a plurality of conductive layers alternatively stacked in a first direction, a plurality of memory pillars MP which extend in the first area in the first direction, a second area which is formed on the logic circuit and has the plurality of first insulating layers 33 and a plurality of second insulating layers alternately stacked in the first direction, and a contact ping CP1 which extends in the second area in the first direction and is connected to the logic circuit.

Abstract: An apparatus for inspecting a defect includes a memory storage and a processing unit coupled to the memory storage. The processing unit is configured to acquire pattern data for one or more patterns implemented on a wafer from a storage device, clip a portion that corresponds to the pattern data from a figure indicated by design data to generate design information and one or more circuit patterns, assign a first set of numbers to the one or more patterns of the pattern data, assign a second set of numbers to the one or more circuit patterns of the design information, generate relation information indicative of one or more correspondences between the first set of numbers and the second set of numbers, verify whether or not the one or more patterns indicated by the pattern data constitute a crucial defect based on the relation information, and send a verification result to a device.

Abstract: According to one embodiment, an SEM inspection apparatus includes an arithmetic processor. The arithmetic processor acquires design data corresponding to an inspection region. The arithmetic processor obtains a resistance component between each of wiring lines included in the inspection region and a portion on a substrate connected thereto, on a basis of the design data. The arithmetic processor obtains a capacitance component between each of the wiring lines included in the inspection region and the portion on the substrate connected thereto, on a basis of the design data. The arithmetic processor color-codes the wiring lines included in the inspection region of the design data, on a basis of a combination of the resistance component and the capacitance component. The arithmetic processor corrects a coordinate deviation between an SEM image and the color-coded design data by performing pattern matching between the color-coded design data and the SEM image.

Abstract: According to one embodiment, an SEM inspection apparatus includes an arithmetic processor. The arithmetic processor acquires design data corresponding to an inspection region. The arithmetic processor obtains a resistance component between each of wiring lines included in the inspection region and a portion on a substrate connected thereto, on a basis of the design data. The arithmetic processor obtains a capacitance component between each of the wiring lines included in the inspection region and the portion on the substrate connected thereto, on a basis of the design data. The arithmetic processor color-codes the wiring lines included in the inspection region of the design data, on a basis of a combination of the resistance component and the capacitance component. The arithmetic processor corrects a coordinate deviation between an SEM image and the color-coded design data by performing pattern matching between the color-coded design data and the SEM image.

Abstract: According to one embodiment, there is provided a memory device which includes a plurality of elements that include three-dimensionally arranged memory cells, a transistor that is electrically connected to at least one of the plurality of elements, an inspection pad that is connected in series to at least one of the plurality of elements through the transistor, and a wiring that is electrically connected to the inspection pad and a gate of the transistor and capable of supplying a common potential to both the inspection pad and the transistor for turning the transistor to an OFF state.

Abstract: A capacitor includes a plurality of first electrode layers stacked in a first direction, a first conductor extending in the first direction through the plurality of first electrode layers, and a first insulating layer extending in the first direction along the first conductor and located between the first conductor and the plurality of first electrode layers. The capacitor includes a first capacitance provided between the first conductor and the plurality of first electrode layers.

Abstract: A capacitor includes a plurality of first electrode layers stacked in a first direction, a first conductor extending in the first direction through the plurality of first electrode layers, and a first insulating layer extending in the first direction along the first conductor and located between the first conductor and the plurality of first electrode layers. The capacitor includes a first capacitance provided between the first conductor and the plurality of first electrode layers.

Abstract: A wafer inspection method includes providing a wafer with at least one position marker; setting a care area around the at least one position marker; detecting a plurality of defects in the wafer by using a surface inspection apparatus identifying the at least one position marker as a defect, the plurality of defects including the defect corresponding to the at least one position marker; and achieving an off-set value of coordinates of the plurality of defects based on the coordinates of the defect corresponding to the at least one position marker and the coordinates of the at least one position marker.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, a plurality of interconnect portions, and at least one columnar member. Each of the plurality of interconnect portions spreads along the stacking direction and a first direction crossing the stacking direction. The plurality of interconnect portions are disposed along the first direction and a second direction crossing the stacking direction and the first direction. The at least one columnar member is provided in the stacked body and extends in the stacking direction. The plurality of interconnect portions include a first interconnect portion and a second interconnect portion adjacent to each other in the first direction. The columnar member is located between a first end portion of the first interconnect portion and a second end portion of the second interconnect portion.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of memory cells arranged on a substrate. The semiconductor memory device includes an interconnect layer including a first interconnect and a second interconnect, the first interconnect extending in a first direction, the second interconnect extending in a second direction, the first direction being tilted with respect to an arrangement direction of the memory cells, the second direction being different from the first direction and tilted with respect to the arrangement direction of the memory cells.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of memory cells arranged on a substrate. The semiconductor memory device includes an interconnect layer including a first interconnect and a second interconnect, the first interconnect extending in a first direction, the second interconnect extending in a second direction, the first direction being tilted with respect to an arrangement direction of the memory cells, the second direction being different from the first direction and tilted with respect to the arrangement direction of the memory cells.

Abstract: In accordance with an embodiment, an inspection apparatus includes first and second charged particle beam application units to apply charged particle beams to a sample, a detector, an image acquiring unit, and a judgment unit. The sample includes a stack structure in which electrically conductive films and insulating films are alternately stacked, electrically conductive layers, first and second contact plugs. The first charged particle beam application unit controls the potential of each electrically conductive film by applying a first charged particle beam to the second contact plugs. The second charged particle beam application unit applies a second charged particle beam to the first contact plugs. The detector detects secondary charged particles from the stack structure and outputs a signal. The image acquiring unit processes the signal to acquire a first image of the sample surface. The judgment unit judges an abnormality of the sample from the acquired first image.

Abstract: A semiconductor pillar which has a first conductivity type and protrudes from a semiconductor substrate, is formed. A bottom diffusion layer having a second conductivity type is formed in the semiconductor substrate around a bottom of the semiconductor pillar. A gate insulator film which covers a side surface of the semiconductor pillar, is formed. A gate electrode which covers the gate insulator film, is formed. A top diffusion layer having the second conductivity type is formed at a top portion of the semiconductor pillar. The top diffusion layer including a semiconductor body is formed by an epitaxial growth which contains an impurity.

Abstract: A crystal material lattice strain evaluation method includes illuminating a sample having a crystal structure with an electron beam in a zone axis direction, and selectively detecting a certain diffracted wave diffracted in a certain direction among a plurality of diffracted waves diffracted by the sample. The method further includes repeating the illuminating step and the selectively detecting step while scanning the sample, and obtaining a strain distribution image in a direction corresponding to the certain diffracted wave from diffraction intensity at each point of the sample.

Abstract: A semiconductor device includes a first island and a first electrode. The first island includes a first semiconductor region, a first insulation region, and a first insulating film. The first semiconductor region has first and second side surfaces adjacent to the first insulation region and the first insulating film, respectively. The first electrode is adjacent to the first insulation region and the first insulating film. The first insulating film is between the first electrode and the first semiconductor region.

Abstract: A semiconductor device is provided, which includes an N well having a peak concentration of 2E+17 atom/cm3 or more in the range of 0.2 to 1 ?m depth from the surface of a P-type semiconductor substrate, and a region provided below the N well, the region containing P-type impurities with higher concentration than concentration of electrons.

Abstract: A crystal material lattice strain evaluation method includes illuminating a sample having a crystal structure with an electron beam in a zone axis direction, and selectively detecting a certain diffracted wave diffracted in a certain direction among a plurality of diffracted waves diffracted by the sample. The method further includes repeating the illuminating step and the selectively detecting step while scanning the sample, and obtaining a strain distribution image in a direction corresponding to the certain diffracted wave from diffraction intensity at each point of the sample.