Abstract: A method of producing a semiconductor device having a plurality of wiring layers forms a first interlayer-insulating film, forms a plurality of grooves for wiring in the first interlayer-insulating film, fills metallic films in the grooves to form wirings, etches the first interlayer-insulating film with the wirings as a mask and removes the interlayer-insulating film between the wirings to provide grooves to be filled, and fills a second interlayer-insulating film made of a material of low dielectric constant in the grooves to be filled.

Abstract: A method of manufacturing a semiconductor device, includes forming a sacrifice film on an etching target film, forming an etching mask on the sacrifice film, etching the etching target film using the etching mask as a mask, removing the sacrifice film to allow the etching mask to adhere to the etching target film, and removing the etching mask.

Abstract: A semiconductor device according to an aspect of the invention comprises a semiconductor substrate, and a capacitor that is provided above the semiconductor substrate and is configured such that a dielectric film is sandwiched between a lower electrode and an upper electrode, the dielectric film being formed of an ABO3 perovskite-type oxide that includes at least one of Pb, Ba and Sr as an A-site element and at least one of Zr, Ti, Ta, Nb, Mg, W, Fe and Co as a B-site element, wherein a radius of curvature of a side wall of the capacitor, when viewed from above or in a film thickness direction, is 250 [nm] or less, and a length of an arc with the radius of curvature is {250 [nm]×?/6 [rad]} or more.

Abstract: A method for manufacturing a semiconductor device including a substrate to be processed having a conductive layer essentially consisting of platinum includes etching the conductive layer, and generating plasma and cleaning the substrate, to which an etching product adhere, by means of ions in the plasma. The cleaning includes heating the substrate to a first temperature, introducing gas, which contains chlorine and nitrogen and in which a ratio of chlorine atoms to nitrogen atoms is 9:1 to 5:5, and applying high-frequency power to an electrode, on which the substrate is placed.

Abstract: A semiconductor memory device, which prevents the penetration of hydrogen or moisture to a ferroelectric capacitor from its surrounding area including a contact plug portion, comprises a ferroelectric capacitor formed above a semiconductor substrate, a first hydrogen barrier film formed on an upper surface of the ferroelectric capacitor to work as a mask in the formation of the ferroelectric capacitor, a second hydrogen barrier film formed on the upper surface and a side face of the ferroelectric capacitor including on the first hydrogen barrier film, and a contact plug disposed through the first and second hydrogen barrier films, and connected to an upper electrode of the ferroelectric capacitor, a side face thereof being surrounded with the hydrogen barrier films.

Abstract: The present invention provides a ferroelectric device relatively free of fences by using a hardmask having high etching selectivity relative to an underlying barrier layer. The present invention also includes a method for suppressing the fences clinging to the sidewalls of ferroelectric devices. Additionally, the present invention provides a ferroelectric device having a hardmask relatively thin compared to an underlying barrier layer when compared to prior art devices.

Abstract: The present invention provides a sidewall oxygen diffusion barrier and a method for fabricating the sidewall oxygen diffusion barrier that reduces the diffusion of oxygen into contact plugs during a CW hole reactive ion etch of a ferroelectric capacitor of an FeRAM device. In one embodiment the sidewall barrier is formed from a substrate fence. In another embodiment, the sidewall barrier is formed by etching back an oxygen barrier.

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor provided above the semiconductor substrate and including a bottom electrode, a dielectric film provided on the bottom electrode, and a top electrode provided on the dielectric film, a mask film provided on the top electrode and used as a mask when a pattern of the capacitor is formed, wherein an inclination of a side surface of the mask film is gentler than an inclination of a side surface of the top electrode and an inclination of a side surface of the dielectric film.

Abstract: An Iridium barrier layer is between a contact plug and a bottom electrode of a capacitor. Etching is performed to pattern the bottom electrode and barrier layer using a fluorine-based recipe resulting in the formation of a first fence clinging to the sidewalls. Next the remaining barrier layer is etched using a CO-based recipe. A second fence is formed clinging to and structurally supported by the first fence. At the same time, the CO-based recipe etches away a substantial portion of the first fence to remove the structural support provided to the second fence. The second fence is therefore lifted-off from the sidewalls leaving the sidewalls substantially free of clinging fences. The etched barrier layer has a sidewall transition. The sidewalls have a relatively low taper angle above the sidewall transition and a relatively steep taper angle below the sidewall transition.

Abstract: A method for manufacturing a semiconductor device including a substrate to be processed having a conductive layer essentially consisting of platinum includes etching the conductive layer, and generating plasma and cleaning the substrate, to which an etching product adhere, by means of ions in the plasma. The cleaning includes heating the substrate to a first temperature, introducing gas, which contains chlorine and nitrogen and in which a ratio of chlorine atoms to nitrogen atoms is 9:1 to 5:5, and applying high-frequency power to an electrode, on which the substrate is placed.

Abstract: There is disclosed a semiconductor device comprising a capacitor comprising a lower electrode provided above a substrate, a capacitor insulating film selectively provided on the lower electrode, and an upper electrode selectively provided above the lower electrode so that the capacitor insulating film can be interposed between the upper and lower electrodes, an electrode protection film formed of oxide conductors containing at least one of metal elements such as Sr, Ti, Ru, Ir and Pt, and provided on the upper electrode, an interlayer insulating film provided on the electrode protection film, an upper layer interconnect wire for the lower electrode provided on the interlayer insulating film, and electrically connected to the lower electrode, and an upper layer interconnect wire for the upper electrode provided on the interlayer insulating film, and electrically connected to the upper electrode.

Abstract: The present invention provides a method for manufacturing a semiconductor device equipped with a capacitor in which a dielectric film is used, wherein a complex oxide is used as a mask material when the dielectric film is etched.

Abstract: An Iridium barrier layer is between a contact plug and a bottom electrode of a capacitor. Etching is performed to pattern the bottom electrode and barrier layer using a fluorine-based recipe resulting in the formation of a first fence clinging to the sidewalls. Next the remaining barrier layer is etched using a CO-based recipe. A second fence is formed clinging to and structurally supported by the first fence. At the same time, the CO-based recipe etches away a substantial portion of the first fence to remove the structural support provided to the second fence. The second fence is therefore lifted-off from the sidewalls leaving the sidewalls substantially free of clinging fences. The etched barrier layer has a sidewall transition. The sidewalls have a relatively low taper angle above the sidewall transition and a relatively steep taper angle below the sidewall transition.

Abstract: A plasma processing apparatus comprises a grounded housing, a thin RF plate electrode, an opposite electrode facing the RF plate electrode, and a RF power source for applying a radio frequency to either the RF plate electrode or the opposite electrode to produce plasma between the two electrodes. If the radio frequency applied to the electrode is f (MHz), the parasitic capacity C (pF) between the grounded portion of the housing and a conductive portion through which the radio frequency propagates is less than 1210*f−0.9. The thickness of the RF plate electrode is 1 mm to 6 mm, and it is supported by a heat sink. The heat sink has a coolant passage in the proximity to the RF plate electrode. The heat sink also has a groove or a cavity in addition to the coolant passage, thereby reducing the value of the dielectric constant of the heat sink as a whole.

Abstract: In semiconductor device fabrication processes which include the formation of hardmask elements 17 including Al2O2, unwanted Al2O3 is left between the hardmask elements 17. The unwanted Al2O3 includes a layer 9 of Al2O3which is not homogenous across the surface of the structure 3 it overlies, and Al2O3 deposits on the sides of the hardmask elements 17. A method is proposed in which any such unwanted Al2O3 between the hardmask elements 17 is removed by a wet etching step in which the unwanted Al2O3 is exposed to an etchant liquid which etches the Al2O3 at a faster rate than other portions of the structure. This step allows the unwanted Al2O3 to be removed substantially completely without causing significant detriment to those other portions of the structure. Subsequently, an RIE etching step can be performed using the hardmask elements 17 as a mask, without the unwanted Al2O3 obstructing the RIE etching step.

Abstract: A plasma processing apparatus comprises a grounded housing, a thin RF plate electrode, an opposite electrode facing the RF plate electrode, and a RF power source for applying a radio frequency to either the RF plate electrode or the opposite electrode to produce plasma between the two electrodes. If the radio frequency applied to the electrode is f (MHz), the parasitic capacity C (pF) between the grounded portion of the housing and a conductive portion through which the radio frequency propagates is less than 1210*f−0.9. The thickness of the RF plate electrode is 1 mm to 6 mm, and it is supported by a heat sink. The heat sink has a coolant passage in the proximity to the RF plate electrode. The heat sink also has a groove or a cavity in addition to the coolant passage, thereby reducing the value of the dielectric constant of the heat sink as a whole.

Abstract: The present invention provides a sidewall oxygen diffusion barrier and method for fabricating the sidewall oxygen diffusion barrier to reduce the diffusion of oxygen to contact plugs during CW hole reactive ion etch processing of a ferroelectric capacitor of an FeRAM device. In one embodiment the sidewall barrier is formed from a substrate fence, while in another embodiment the sidewall barrier is formed by etching back an oxygen barrier.

Abstract: The present invention provides a ferroelectric device relatively free of fences by using a hardmask having high etching selectivity relative to an underlying barrier layer. The present invention also includes a method for suppressing the fences clinging to the sidewalls of ferroelectric devices. Additionally, the present invention provides a ferroelectric device having a hardmask relatively thin compared to an underlying barrier layer when compared to prior art devices.

Abstract: A process for the fabrication of a ferrocapacitor comprising depositing a first mask element 7 over a structure having a bottom electrode 1, a ferroelectric layer 3 and a top electrode 5. RIE etching is performed to remove portions of the top electrode 5 and the ferroelectric layer 3. Then a second hard mask element 9 is deposited over the first hardmask element. The second hard mask element is rounded by an etch back process, and its taper angle is controlled to be in the range 75-87°. A second RIE etching process is performed to remove portions of the bottom electrode 1. Due to the rounding of the second hard mask elements 9 low residues are formed on the sides of the etched bottom electrode 1.

Abstract: A semiconductor device having a plurality of wiring layers includes: a first insulating film firstly formed in layer; a first wiring layer having a plurality of wirings, formed on the first insulating film; a second wiring layer having a plurality of wirings, formed on or over the first wiring layer; and a second insulating film provided on the first insulating film formed as having a plane surface and the first wiring layer, and formed between adjacent wirings of the second wiring layer, located under the second wiring layer but on the first insulating film and the first wiring layer, at least a part of the second insulating film existing between the first and second wiring layers having a relative dielectric constant lower than a relative dielectric constant of the first insulating film.