Patents by Inventor Kazuhisa Uchida

Kazuhisa Uchida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12100555
    Abstract: A multilayer ceramic capacitor includes first dielectric ceramic layers each with a thickness of about 0.48 ?m or more and about 0.50 ?m or less in the lamination direction, and additional dielectric ceramic layers each with a thickness of about 10 ?m or more and about 15 ?m or less in the width direction. A number of dielectric particles in each first dielectric ceramic layer in a thickness direction is three or more and six or less. A number of dielectric particles in each additional dielectric ceramic layer in a thickness direction is 100 or more and 150 or less. When the number of dielectric particles in each of first dielectric ceramic layer is NT, and the number of dielectric particles in each additional dielectric ceramic layer is NW, a ratio of NT to NW is about 1:23.08 or more and about 1:46.15 or less.
    Type: Grant
    Filed: August 24, 2023
    Date of Patent: September 24, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoshiyuki Abe, Kazuhisa Uchida
  • Patent number: 12080484
    Abstract: A multilayer ceramic capacitor that includes a ceramic body including a stack of a plurality of dielectric layers and a plurality of first and second internal electrodes; and first and second external electrodes provided at each of both end faces of the ceramic body. Each of the plurality of dielectric layers contain Ba, Ti, P and Si. The plurality of dielectric layers include an outer dielectric layer located on an outermost side in the stacking direction; an inner dielectric layer located between the first and second internal electrodes; and a side margin portion in a region where the first and second internal electrodes do not exist. In at least one of the outer dielectric layer, the inner dielectric layer and the side margin portion, the P and the Si segregate in at least one of grain-boundary triple points of three ceramic particles.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: September 3, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Akihiro Tsuru, Kazuhisa Uchida
  • Patent number: 12040138
    Abstract: A multilayer ceramic capacitor includes a multilayer body including dielectric ceramic layers and internal electrode layers laminated alternately in a lamination direction, and a pair of external electrodes on both end portions in the length direction of the multilayer body and respectively connected to the internal electrode layers. The pair of external electrodes each include a base region covering at least each of the first and second end surfaces, connected to the internal electrode layers, and including Cu as a main component, a cover region on the base region to cover the base region, and including Ag as a main component, and a reaction region between the base region and the cover region including Cu included in the base region and Ag included in the cover region reacting with each other.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: July 16, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kazuhisa Uchida, Yukie Watanabe
  • Publication number: 20230395324
    Abstract: A multilayer ceramic capacitor includes first dielectric ceramic layers each with a thickness of about 0.48 ?m or more and about 0.50 ?m or less in the lamination direction, and additional dielectric ceramic layers each with a thickness of about 10 ?m or more and about 15 ?m or less in the width direction. A number of dielectric particles in each first dielectric ceramic layer in a thickness direction is three or more and six or less. A number of dielectric particles in each additional dielectric ceramic layer in a thickness direction is 100 or more and 150 or less. When the number of dielectric particles in each of first dielectric ceramic layer is NT, and the number of dielectric particles in each additional dielectric ceramic layer is NW, a ratio of NT to NW is about 1:23.08 or more and about 1:46.15 or less.
    Type: Application
    Filed: August 24, 2023
    Publication date: December 7, 2023
    Inventors: Yoshiyuki ABE, Kazuhisa UCHIDA
  • Publication number: 20230386744
    Abstract: A multilayer ceramic capacitor includes a multilayer body including the dielectric ceramic layers and the internal electrode layers which are laminated, and external electrodes connected to the internal electrode layers. The multilayer body includes segregation including Si as a main component in a vicinity of an end of the internal electrode layer in a width direction. An average particle size of the dielectric particles in the vicinity of the end of the internal electrode layer in the width direction in the dielectric ceramic layer is smaller than an average particle size of a dielectric particles in a central portion of the internal electrode layer in the width direction in the dielectric ceramic layer.
    Type: Application
    Filed: August 14, 2023
    Publication date: November 30, 2023
    Inventor: Kazuhisa UCHIDA
  • Patent number: 11810724
    Abstract: A multilayer ceramic capacitor includes a base body including first and second main surfaces, first and second side surfaces, first and second end surfaces, and dielectric layers and internal electrode layers, and external electrodes at the first and second end surfaces, and electrically connected to the internal electrode layers. The base body includes an inner layer, first and second outer layers, first and second side margin portions. The dielectric layers in the inner layer and the first and second outer layers include main crystal grains including barium and titanium, and with respect to 100 parts by mol of titanium, nickel in an amount of about 0.2 to about 3.0 parts by mol, and at least one rare earth element selected from yttrium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium in an amount of about 0.6 parts to about 2.0 parts by mol.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: November 7, 2023
    Assignee: MURATA MANUFACTURING CO., LTD
    Inventors: Shinya Isota, Takehisa Sasabayashi, Kazuhisa Uchida, Hideyuki Hashimoto, Yuta Oshima
  • Publication number: 20230346944
    Abstract: A virus inactivation method is provided. The method includes irradiating a solution containing an artificially expressed antibody or antibody fragment with ultraviolet rays in the presence of a radical scavenger. The irradiating only aggregates 5% or less of the antibody or antibody fragment. A wavelength of the ultraviolet rays is 200 nm or longer and 315 nm or shorter. An irradiation amount of the ultraviolet rays is 300 mJ/cm2 or more. An irradiation time of the ultraviolet rays is 3 minutes or less. A concentration of the radical scavenger in the solution is 0.03 mM or more.
    Type: Application
    Filed: June 20, 2023
    Publication date: November 2, 2023
    Applicants: NATIONAL UNIVERSITY CORPORATION KOBE UNIVERSITY, ABLE Corporation
    Inventors: Kazuhisa UCHIDA, Shutaro ISHIKAWA, Satoshi TOMITA, Kensaku KANADA
  • Publication number: 20230317374
    Abstract: A multilayer ceramic capacitor includes a multilayer body including dielectric layers and internal electrode layers, and external electrodes. The multilayer body includes side margin portions made of a dielectric. In the internal electrode layers, a width of an extension electrode portion is smaller than a width of a counter electrode portion. The side margin portions each include Ba and Ti as a main component and Mg as a sub component. The Mg content is about 0.2 mol% or more and about 2.0 mol% or less with respect to 100 mol of Ti. The internal electrode layers each include Ni as a main component, and an end portion of the counter electrode portion includes Mg as a sub component. The Mg content is about 0.13 mol% or more and about 0.39 mol% or less with respect to 100 mol of Ni.
    Type: Application
    Filed: February 14, 2023
    Publication date: October 5, 2023
    Inventors: Natsuko OKUBO, Akito MORI, Kazuhisa UCHIDA
  • Patent number: 11776749
    Abstract: A multilayer ceramic capacitor includes a multilayer body including the dielectric ceramic layers and the internal electrode layers which are laminated, and external electrodes connected to the internal electrode layers. The multilayer body includes segregation including Si as a main component in a vicinity of an end of the internal electrode layer in a width direction. An average particle size of the dielectric particles in the vicinity of the end of the internal electrode layer in the width direction in the dielectric ceramic layer is smaller than an average particle size of a dielectric particles in a central portion of the internal electrode layer in the width direction in the dielectric ceramic layer.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: October 3, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Kazuhisa Uchida
  • Patent number: 11776751
    Abstract: A multilayer ceramic capacitor includes first dielectric ceramic layers each with a thickness of about 0.48 ?m or more and about 0.50 ?m or less in the lamination direction, and additional dielectric ceramic layers each with a thickness of about 10 ?m or more and about 15 ?m or less in the width direction. A number of dielectric particles in each first dielectric ceramic layer in a thickness direction is three or more and six or less. A number of dielectric particles in each additional dielectric ceramic layer in a thickness direction is 100 or more and 150 or less. When the number of dielectric particles in each of first dielectric ceramic layer is NT, and the number of dielectric particles in each additional dielectric ceramic layer is NW, a ratio of NT to NW is about 1:23.08 or more and about 1:46.15 or less.
    Type: Grant
    Filed: February 3, 2022
    Date of Patent: October 3, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoshiyuki Abe, Kazuhisa Uchida
  • Publication number: 20230019604
    Abstract: A multilayer ceramic capacitor includes a multilayer body including dielectric ceramic layers and internal electrode layers laminated alternately in a lamination direction, and a pair of external electrodes on both end portions in the length direction of the multilayer body and respectively connected to the internal electrode layers. The pair of external electrodes each include a base region covering at least each of the first and second end surfaces, connected to the internal electrode layers, and including Cu as a main component, a cover region on the base region to cover the base region, and including Ag as a main component, and a reaction region between the base region and the cover region including Cu included in the base region and Ag included in the cover region reacting with each other.
    Type: Application
    Filed: June 27, 2022
    Publication date: January 19, 2023
    Inventors: Kazuhisa UCHIDA, Yukie WATANABE
  • Patent number: 11443895
    Abstract: A multilayer ceramic capacitor includes a laminate including a dielectric ceramic layer and first and second electrode layers laminated in a lamination direction, and first and second external electrodes respectively connected to the first and second internal electrode layers. The laminate includes a central layer portion, a peripheral layer portion sandwiching the central layer portion, and a side margin sandwiching the central layer portion and the peripheral layer portion. The first and second internal electrode layers and the first and second external electrodes include Ni. In a cross section including the lamination direction and a width direction, a Ni content of the peripheral layer portion is larger at a surface portion than at a central portion in a thickness direction, and a Ni content of the side margin is larger at a surface portion than at a central portion in a thickness direction of the side margin.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: September 13, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Akitaka Doi, Akito Mori, Kazuhisa Uchida
  • Publication number: 20220262568
    Abstract: A multilayer ceramic capacitor includes first dielectric ceramic layers each with a thickness of about 0.48 ?m or more and about 0.50 ?m or less in the lamination direction, and additional dielectric ceramic layers each with a thickness of about 10 ?m or more and about 15 ?m or less in the width direction. A number of dielectric particles in each first dielectric ceramic layer in a thickness direction is three or more and six or less. A number of dielectric particles in each additional dielectric ceramic layer in a thickness direction is 100 or more and 150 or less. When the number of dielectric particles in each of first dielectric ceramic layer is NT, and the number of dielectric particles in each additional dielectric ceramic layer is NW, a ratio of NT to NW is about 1:23.08 or more and about 1:46.15 or less.
    Type: Application
    Filed: February 3, 2022
    Publication date: August 18, 2022
    Inventors: Yoshiyuki ABE, Kazuhisa UCHIDA
  • Publication number: 20220238276
    Abstract: A multilayer ceramic capacitor includes a multilayer body including the dielectric ceramic layers and the internal electrode layers which are laminated, and external electrodes connected to the internal electrode layers. The multilayer body includes segregation including Si as a main component in a vicinity of an end of the internal electrode layer in a width direction. An average particle size of the dielectric particles in the vicinity of the end of the internal electrode layer in the width direction in the dielectric ceramic layer is smaller than an average particle size of a dielectric particles in a central portion of the internal electrode layer in the width direction in the dielectric ceramic layer.
    Type: Application
    Filed: January 10, 2022
    Publication date: July 28, 2022
    Inventor: Kazuhisa UCHIDA
  • Publication number: 20220102076
    Abstract: A multilayer ceramic capacitor includes a base body including first and second main surfaces, first and second side surfaces, first and second end surfaces, and dielectric layers and internal electrode layers, and external electrodes at the first and second end surfaces, and electrically connected to the internal electrode layers. The base body includes an inner layer, first and second outer layers, first and second side margin portions. The dielectric layers in the inner layer and the first and second outer layers include main crystal grains including barium and titanium, and with respect to 100 parts by mol of titanium, nickel in an amount of about 0.2 to about 3.0 parts by mol, and at least one rare earth element selected from yttrium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium in an amount of about 0.6 parts to about 2.0 parts by mol.
    Type: Application
    Filed: August 25, 2021
    Publication date: March 31, 2022
    Inventors: Shinya ISOTA, Takehisa SASABAYASHI, Kazuhisa UCHIDA, Hideyuki HASHIMOTO, Yuta OSHIMA
  • Patent number: 11264174
    Abstract: A multilayer ceramic capacitor that includes a ceramic body including a stack of a plurality of dielectric layers and a plurality of first and second internal electrodes; and first and second external electrodes provided at each of both end faces of the ceramic body. Each of the plurality of dielectric layers contain Ba, Ti, P and Si. The plurality of dielectric layers include an outer dielectric layer located on an outermost side in the stacking direction; an inner dielectric layer located between the first and second internal electrodes; and a side margin portion in a region where the first and second internal electrodes do not exist. In at least one of the outer dielectric layer, the inner dielectric layer and the side margin portion, the P and the Si segregate in at least one of grain-boundary triple points of three ceramic particles.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: March 1, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Akihiro Tsuru, Kazuhisa Uchida
  • Patent number: 11257627
    Abstract: A multilayer ceramic capacitor includes a laminate including a dielectric ceramic layer and first and second internal electrode layers laminated in a lamination direction, and first and second external electrode connected to the internal electrode layers. The laminate includes a central layer portion, a peripheral layer portion sandwiching the central layer portion, and a side margin sandwiching the central layer portion and the peripheral layer portion. The side margin includes an inner layer and an outer layer. In a cross section including a lamination direction and a width direction obtained by cutting the laminate at the center in a longitudinal direction of the laminate, the ceramic grains in the dielectric ceramic layer between ends of the internal electrode layers in the width direction have a smaller diameter than the ceramic grains in the dielectric ceramic layer at the center of the central layer portion in the width direction.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: February 22, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Kazuhisa Uchida
  • Publication number: 20220028620
    Abstract: A multilayer ceramic capacitor that includes a ceramic body including a stack of a plurality of dielectric layers and a plurality of first and second internal electrodes; and first and second external electrodes provided at each of both end faces of the ceramic body. Each of the plurality of dielectric layers contain Ba, Ti, P and Si. The plurality of dielectric layers include an outer dielectric layer located on an outermost side in the stacking direction; an inner dielectric layer located between the first and second internal electrodes; and a side margin portion in a region where the first and second internal electrodes do not exist. In at least one of the outer dielectric layer, the inner dielectric layer and the side margin portion, the P and the Si segregate in at least one of grain-boundary triple points of three ceramic particles.
    Type: Application
    Filed: October 12, 2021
    Publication date: January 27, 2022
    Inventors: Akihiro Tsuru, Kazuhisa Uchida
  • Patent number: 11081279
    Abstract: A multilayer ceramic capacitor that includes outer electrodes and a multilayer body having stacked inner electrode layers and dielectric layers. The dielectric layers in an effective section contain, relative to 100 parts by mole of Ti, 0.7 to 1.2 parts by mole of Si, 0.9 to 1.1 parts by mole of Dy, 0.24 to 0.34 parts by mole of Mg, 0.17 to 0.23 parts by mole of Al, 0.09 to 0.11 parts by mole of Mn, and 0.04 to 0.06 parts by mole of V. The dielectric layers have a Ba/Ti molar ratio of 1.0073 to 1.0083.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: August 3, 2021
    Inventors: Kazuhisa Uchida, Naoto Muranishi
  • Publication number: 20200312555
    Abstract: A multilayer ceramic capacitor includes a laminate including a dielectric ceramic layer and first and second electrode layers laminated in a lamination direction, and first and second external electrodes respectively connected to the first and second internal electrode layers. The laminate includes a central layer portion, a peripheral layer portion sandwiching the central layer portion, and a side margin sandwiching the central layer portion and the peripheral layer portion. The first and second internal electrode layers and the first and second external electrodes include Ni. In a cross section including the lamination direction and a width direction, a Ni content of the peripheral layer portion is larger at a surface portion than at a central portion in a thickness direction, and a Ni content of the side margin is larger at a surface portion than at a central portion in a thickness direction of the side margin.
    Type: Application
    Filed: March 18, 2020
    Publication date: October 1, 2020
    Inventors: Akitaka DOI, Akito MORI, Kazuhisa UCHIDA