Abstract: It is an object of the present technology to provide a solid-state image sensor capable of reducing display unevenness of a captured image. A solid-state image sensor includes a first substrate that includes a photoelectric conversion unit, a transfer gate unit that is connected to the photoelectric conversion unit, an FD unit that is connected to the transfer gate unit, and an interlayer insulating film that covers the photoelectric conversion unit, the transfer gate unit, and the FD unit. The solid-state image sensor further includes a second substrate that includes an amplifier transistor and is disposed to be adjacent to the interlayer insulating film, the amplifier transistor constituting a part of a pixel transistor connected to the FO unit via the interlayer insulating film and including a back gate unit.

Abstract: A photoelectric conversion device according to an embodiment of the present disclosure includes: a first semiconductor layer in which a transfer transistor is provided; a second semiconductor layer in which a pixel transistor is provided; and a wiring layer in which a gate wiring line coupled to a gate of the transfer transistor is provided. A portion or all of the pixel transistor is disposed, in plan view, in a region between a first gate wiring line and a second gate wiring line. The first gate wiring line is coupled to the gate of the transfer transistor in one of two pixels adjacent to each other. The second gate wiring line is coupled to the gate of the transfer transistor in another of the two pixels adjacent to each other.

Abstract: Described herein are the design and fabrication of Group III trioxides, such as ?-Ga2O3, trench-MOS barrier Schottky (TMBS) structures with high voltage (>1 kV), low leakage capabilities, while addressing on the necessary methods to meet the requirements unique to Group III trioxides, such as ?-Ga2O3.

Abstract: Improvement of noise characteristics is achievable. A solid-state imaging device according to an embodiment includes a plurality of photoelectric conversion elements (333) arranged in a two-dimensional grid shape in a matrix direction and each generating a charge corresponding to a received light amount, and a detection unit (400) that detects a photocurrent produced by the charge generated in each of the plurality of photoelectric conversion elements. A chip (201a) on which the photoelectric conversion elements are disposed and a chip (201b) on which at least a part of the detection unit is disposed are different from each other.

Abstract: A vertical gallium oxide (Ga2O3) device having a substrate, an n-type Ga2O3 drift layer on the substrate, an, n-type semiconducting channel extending from the n-type Ga2O3 drift layer, the channel being one of fin-shaped or nanowire shaped, an n-type source layer disposed on the channel; the source layer has a higher doping concentration than the channel, a first dielectric layer on the n-type Ga2O3 drift layer and on sidewalls of the n-type semiconducting channel, a conductive gate layer deposited on the first dielectric layer and insulated from the n-type source layer, n-type semiconducting channel as well as n-type Ga2O3 drift layer, a second dielectric layer deposited over the conductive gate layer, covering completely the conductive gate layer on channel sidewalls and an ohmic source contact deposited over the n-type source layer and over at least a part of the second dielectric layer; the source contact being configured not to be in electrical contact with the conductive gate layer.

Abstract: A vertical gallium oxide (Ga2O3) device having a substrate, an n-type Ga2O3 drift layer on the substrate, an, n-type semiconducting channel extending from the n-type Ga2O3 drift layer, the channel being one of fin-shaped or nanowire shaped, an n-type source layer disposed on the channel; the source layer has a higher doping concentration than the channel, a first dielectric layer on the n-type Ga2O3 drift layer and on sidewalls of the n-type semiconducting channel, a conductive gate layer deposited on the first dielectric layer and insulated from the n-type source layer, n-type semiconducting channel as well as n-type Ga2O3 drift layer, a second dielectric layer deposited over the conductive gate layer, covering completely the conductive gate layer on channel sidewalls and an ohmic source contact deposited over the n-type source layer and over at least a part of the second dielectric layer; the source contact being configured not to be in electrical contact with the conductive gate layer.

Abstract: A method for achieving voltage-controlled gate-modulated light emission using monolithic integration of fin- and nanowire-n-i-n vertical FETs with bottom-tunnel junction planar InGaN LEDs is described. This method takes advantage of the improved performance of bottom-tunnel junction LEDs over their top-tunnel junction counterparts, while allowing for strong gate control on a low-cross-sectional area fin or wire without sacrificing LED active area as in lateral integration designs. Electrical modulation of 5 orders, and an order of magnitude of optical modulation are achieved in the device.

Abstract: Improvement of noise characteristics is achievable. A solid-state imaging device according to an embodiment includes a plurality of photoelectric conversion elements (333) arranged in a two-dimensional grid shape in a matrix direction and each generating a charge corresponding to a received light amount, and a detection unit (400) that detects a photocurrent produced by the charge generated in each of the plurality of photoelectric conversion elements. A chip (201a) on which the photoelectric conversion elements are disposed and a chip (201b) on which at least a part of the detection unit is disposed are different from each other.

Abstract: Improvement of noise characteristics is achievable. A solid-state imaging device according to an embodiment includes a plurality of photoelectric conversion elements (333) arranged in a two-dimensional grid shape in a matrix direction and each generating a charge corresponding to a received light amount, and a detection unit (400) that detects a photocurrent produced by the charge generated in each of the plurality of photoelectric conversion elements. A chip (201a) on which the photoelectric conversion elements are disposed and a chip (201b) on which at least a part of the detection unit is disposed are different from each other.

Abstract: A device that includes a metal(III)-polar III-nitride substrate having a first surface opposite a second surface, a tunnel junction formed on one of the first surface or a buffer layer disposed on the first surface, a p-type III-nitride layer formed directly on the tunnel junction, and a number of material layers; a first material layer formed on the p-type III-nitride layer, each subsequent layer disposed on a preceding layer, where one layer from the number of material layers is patterned into a structure, that one layer being a III-nitride layer. Methods for forming the device are also disclosed.

Abstract: Improvement of noise characteristics is achievable. A solid-state imaging device according to an embodiment includes a plurality of photoelectric conversion elements (333) arranged in a two-dimensional grid shape in a matrix direction and each generating a charge corresponding to a received light amount, and a detection unit (400) that detects a photocurrent produced by the charge generated in each of the plurality of photoelectric conversion elements. A chip (201a) on which the photoelectric conversion elements are disposed and a chip (201b) on which at least a part of the detection unit is disposed are different from each other.

Abstract: Described herein are the design and fabrication of Group III trioxides, such as ?-Ga2O3, trench-MOS barrier Schottky (TMBS) structures with high voltage (>1 kV), low leakage capabilities, while addressing on the necessary methods to meet the re-quirements unique to Group III trioxides, such as ?-Ga2O3.

Abstract: It is an object of the present technology to provide a solid-state image sensor capable of reducing display unevenness of a captured image. A solid-state image sensor includes: a first substrate that includes a photoelectric conversion unit, a transfer gate unit that is connected to the photoelectric conversion unit, an FD unit that is connected to the transfer gate unit, and an interlayer insulating film that covers the photoelectric conversion unit, the transfer gate unit, and the FD unit; and a second substrate that includes an amplifier transistor and is disposed to be adjacent to the interlayer insulating film, the amplifier transistor constituting a part of a pixel transistor connected to the FD unit via the interlayer insulating film and including a back gate unit.

Abstract: A device that includes a metal(III)-polar III-nitride substrate having a first surface opposite a second surface, a tunnel junction formed on one of the first surface or a buffer layer disposed on the first surface, a p-type III-nitride layer formed directly on the tunnel junction, and a number of material layers; a first material layer formed on the p-type III-nitride layer, each subsequent layer disposed on a preceding layer, where one layer from the number of material layers is patterned into a structure, that one layer being a III-nitride layer. Methods for forming the device are also disclosed.

Abstract: A vertical gallium oxide (Ga2O3) device having a substrate, an n-type Ga2O3 drift layer on the substrate, an, n-type semiconducting channel extending from the n-type Ga2O3 drift layer, the channel being one of fin-shaped or nanowire shaped, an n-type source layer disposed on the channel; the source layer has a higher doping concentration than the channel, a first dielectric layer on the n-type Ga2O3 drift layer and on sidewalls of the n-type semiconducting channel, a conductive gate layer deposited on the first dielectric layer and insulated from the n-type source layer, n-type semiconducting channel as well as n-type Ga2O3 drift layer, a second dielectric layer deposited over the conductive gate layer, covering completely the conductive gate layer on channel sidewalls and an ohmic source contact deposited over the n-type source layer and over at least a part of the second dielectric layer; the source contact being configured not to be in electrical contact with the conductive gate layer.

Abstract: A solid-state imaging device includes a substrate, a photoelectric conversion section, a first impurity layer having a carrier polarity of a second conductivity type, a charge-to-voltage converting section, an amplifying section, and a second impurity layer having a carrier polarity of the second conductivity type. The second impurity layer is disposed in a region between the photoelectric conversion section and the amplifying section. The second impurity concentration of the second P-type impurity layer is made higher than the first impurity concentration of the first impurity layer.

Abstract: A solid-state imaging device includes a substrate, a photoelectric conversion section, a first impurity layer having a carrier polarity of a second conductivity type, a charge-to-voltage converting section, an amplifying section, and a second impurity layer having a carrier polarity of the second conductivity type. The second impurity layer is disposed in a region between the photoelectric conversion section and the amplifying section. The second impurity concentration of the second P-type impurity layer is made higher than the first impurity concentration of the first impurity layer.

Abstract: There is provided a solid-state image sensor including a plurality of unit pixels arranged thereon, the plurality of unit pixels each including a light receiving section which stores a charge generated by photoelectric conversion, a signal storage section which is connected to the light receiving section and has a structure of a MOS capacitor, and a signal output section to which a gate electrode of the MOS capacitor is connected.

Abstract: A solid-state imaging device includes a substrate, a photoelectric conversion section, a first impurity layer having a carrier polarity of a second conductivity type, a charge-to-voltage converting section, an amplifying section, and a second impurity layer having a carrier polarity of the second conductivity type. The second impurity layer is disposed in a region between the photoelectric conversion section and the amplifying section. The second impurity concentration of the second P-type impurity layer is made higher than the first impurity concentration of the first impurity layer.

Abstract: A nitride-based field effect transistor (FET) comprises a compositionally graded and polarization induced doped p-layer underlying at least one gate contact and a compositionally graded and doped n-channel underlying a source contact. The n-channel is converted from the p-layer to the n-channel by ion implantation, a buffer underlies the doped p-layer and the n-channel, and a drain underlies the buffer.