Abstract: A ferroelectric memory device includes a simple matrix type memory cell array. Provided that the maximum absolute value of a voltage applied between a first signal electrode and a second signal electrode is Vs, polarization P of a ferroelectric capacitor formed of the first electrode, the second electrode, and ferroelectric layer is within the range of 0.1P(+Vs)<P(?1/3Vs) when the applied voltage is changed from +Vs to ?1/3Vs, and 0.1P(?Vs)>P(+1/3Vs) when the applied voltage is changed from ?Vs to +1/3Vs.

Abstract: A first electrode layer 12, a first piezoelectric film layer 13, a second electrode layer 14, a second piezoelectric film layer 15, and a third electrode layer 16 are layered in that order on a substrate 11; these are constrained so as not to expand or contract in a thickness direction and a piezoelectric transducer is constructed thereby.

Abstract: An object of the present invention is to provide compounds having potent antitumor activity. The compounds according to the present invention are compounds represented by formula (I) or pharmaceutically acceptable salts or solvates thereof: wherein X and Z represent CH or N; Y represents O or S; R1, R2, and R3 represent H, alkoxy or the like; R4 represents H; R5, R6, R7, and R8 represent H, halogen, alkoxy or the like; R9 and R10 represent H, alkyl or the like; and R11 represents optionally substituted azolyl.

Abstract: An object of the present invention is to provide compounds having potent antitumor activity.

Abstract: A ferroelectric memory device includes a memory cell array and a peripheral circuit section. The memory cell array, in which memory cells are arranged in a matrix, includes first signal electrodes, second signal electrodes which are arranged in a direction so as to intersect the first signal electrodes, and a ferroelectric layer disposed at least at intersection regions between the first signal electrodes and the second signal electrodes. The peripheral circuit section includes circuits for selectively allowing information to be written into or read from the memory cells, such as a first driver circuit, a second driver circuit, and a signal detection circuit. The memory cell array and the peripheral circuit section are disposed in different layers so as to be layered. This ferroelectric memory device can significantly increase the degree of integration of the memory cells and decrease the chip area.

Abstract: Provided are a memory cell array including ferroelectric capacitors with improved characteristics, a method for making the same, and a ferroelectric memory device including the memory cell of the present invention.

Abstract: A first electrode layer 12, a first piezoelectric film layer 13, a second electrode layer 14, a second piezoelectric film layer 15, and a third electrode layer 16 are layered in that order on a substrate 11; these are constrained so as pot to expand or contract in a thickness direction and a piezoelectric transducer is constructed thereby.

Abstract: A ferroelectric memory device of the present invention includes a memory cell array in which memory cells are arranged in a matrix having first signal electrodes, second signal electrodes arranged in a direction intersecting the first signal electrodes, and a ferroelectric layer disposed at least in intersection regions between the first signal electrodes and the second signal electrodes, and a peripheral circuit section for selectively writing information into or reading information from the memory cell. The memory cell array and the peripheral circuit section are formed in different layers. The peripheral circuit section is formed in a region outside the memory cell array.

Abstract: A ferroelectric memory device includes a memory cell array and a peripheral circuit section. The memory cell array, in which memory cells are arranged in a matrix, includes first signal electrodes, second signal electrodes which are arranged in a direction so as to intersect the first signal electrodes, and a ferroelectric layer disposed at least at intersection regions between the first signal electrodes and the second signal electrodes. The peripheral circuit section includes circuits for selectively allowing information to be written into or read from the memory cells, such as a first driver circuit, a second driver circuit, and a signal detection circuit. The memory cell array and the peripheral circuit section are disposed in different layers so as to be layered. This ferroelectric memory device can significantly increase the degree of integration of the memory cells and decrease the chip area.

Abstract: The present invention relates to a ferroelectric memory having a matrix-type memory cell array which has an excellent degree of integration, in which the angularity of the ferroelectric layer's hysteresis curve is improved. A ferroelectric memory having both integration and memory characteristics in which the angularity of the ferroelectric layer's hysteresis curve is improved is realized as follows. Namely, a structure is employed in which the memory cell array and the peripheral circuit are in a plane separated from one another, and the ferroelectric layer is made to undergo epitaxial growth on to a Si single crystal via a buffer and the first signal electrodes.

Abstract: A ferroelectric memory device of the present invention includes a memory cell array in which memory cells are arranged in a matrix having first signal electrodes, second signal electrodes arranged in a direction intersecting the first signal electrodes, and a ferroelectric layer disposed at least in intersection regions between the first signal electrodes and the second signal electrodes, and a peripheral circuit section for selectively writing information into or reading information from the memory cell. The memory cell array and the peripheral circuit section are formed in different layers. The peripheral circuit section is formed in a region outside the memory cell array.

Abstract: A ferroelectric memory device includes memory cells including ferroelectric capacitors formed in regions in which first signal electrodes intersect second signal electrodes. Information is written into a selected memory cell by applying a write voltage between one of the first signal electrodes and one of the second signal electrodes in the memory cell. Information is read from the selected memory cell by applying a read voltage between one of the first signal electrodes and one of the second signal electrodes in the memory cell. Provided that the write voltage is ±Vs and the read voltage is either +Vs or −Vs, |Vs| is less than the absolute value of a saturation voltage at which remanent polarization of the ferroelectric capacitors is saturated.

Abstract: A ferroelectric memory device includes a simple matrix type memory cell array. Provided that the maximum absolute value of a voltage applied between a first signal electrode and a second signal electrode is Vs, polarization P of a ferroelectric capacitor formed of the first signal electrode, the second signal electrode, and ferroelectric layer is within the range of 0.1P(+Vs)<P(−⅓Vs) when the applied voltage is changed from +Vs to −⅓Vs, and 0.1P(−Vs)>P(+⅓Vs) when the applied voltage is changed from −Vs to +⅓Vs.

Abstract: A ferroelectric memory device includes a memory cell array and a peripheral circuit section. The memory cell array, in which memory cells are arranged in a matrix, includes first signal electrodes, second signal electrodes which are arranged in a direction so as to intersect the first signal electrodes, and a ferroelectric layer disposed at least at intersection regions between the first signal electrodes and the second signal electrodes. The peripheral circuit section includes circuits for selectively allowing information to be written into or read from the memory cells, such as a first driver circuit, a second driver circuit, and a signal detection circuit. The memory cell array and the peripheral circuit section are disposed in different layers so as to be layered. This ferroelectric memory device can significantly increase the degree of integration of the memory cells and decrease the chip area.

Abstract: A ferroelectric memory device includes a simple matrix type memory cell array. Provided that the maximum absolute value of a voltage applied between a first signal electrode and a second signal electrode is Vs, polarization P of a ferroelectric capacitor formed of the first electrode, the second electrode, and ferroelectric layer is within the range of 0.1P(+Vs)<P(−1/3Vs) when the applied voltage is changed from +Vs to −1/3Vs, and 0.1P(−Vs)>P(+1/3Vs) when the applied voltage is changed from −Vs to +1/3Vs.

Abstract: The present invention relates to: a memory cell array which is capable of decreasing the parasitic capacitance of signal electrodes and has ferroelectric layers making up ferroelectric capacitors and having a predetermined pattern; a method of fabricating the memory cell array, and a ferroelectric memory device. In the memory cell array, memory cells formed of ferroelectric capacitors are arranged in a matrix. The ferroelectric capacitors include first signal electrodes, second signal electrodes arranged in a direction intersecting the first signal electrodes, and ferroelectric layers disposed linearly along either the first signal electrodes or the second signal electrodes. Alternatively, the ferroelectric layers may be disposed only in intersection areas of the first and second signal electrodes.

Abstract: A ferroelectric memory device includes a memory cell array in which a plurality of memory cells having at least one ferroelectric capacitor are arranged. Three or more values of data (Pr(0), P1(1), and −Pr(2), for example) can be selectively stored in the ferroelectric capacitor by applying voltages having three or more different values for setting three or more polarization states in the ferroelectric capacitor.

Abstract: The present invention relates to: a memory cell array which is capable of decreasing the parasitic capacitance or load capacitance of signal electrodes and has ferroelectric layers making up ferroelectric capacitors and having a predetermined pattern; a method of fabricating the memory cell array, and a ferroelectric memory device. In the memory cell array, memory cells formed of ferroelectric capacitors are arranged in a matrix. The ferroelectric capacitors include first signal electrodes, second signal electrodes arranged in a direction intersecting the first signal electrodes, and ferroelectric layers disposed linearly along either the first signal electrodes or the second signal electrodes. Alternatively, the ferroelectric layers may be disposed only in intersection areas of the first and second signal electrodes.

Abstract: An object of the present invention is to provide compounds having potent antitumor activity.

Abstract: A ferroelectric memory device includes memory cells including ferroelectric capacitors formed in regions in which first signal electrodes intersect second signal electrodes. Information is written into a selected memory cell by applying a write voltage between one of the first signal electrodes and one of the second signal electrodes in the memory cell. Information is read from the selected memory cell by applying a read voltage between one of the first signal electrodes and one of the second signal electrodes in the memory cell. Provided that the write voltage is ±Vs and the read voltage is either +Vs or −Vs, |Vs| is less than the absolute value of a saturation voltage at which remanent polarization of the ferroelectric capacitors is saturated.