Patents by Inventor Kazumasa Hasegawa

Kazumasa Hasegawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020159306
    Abstract: A ferroelectric memory device includes a simple matrix type memory cell array. Provided that the maximum absolute value of a voltage applied between a first signal electrode and a second signal electrode is Vs, polarization P of a ferroelectric capacitor formed of the first electrode, the second electrode, and ferroelectric layer is within the range of 0.1 P(+Vs)<P(−⅓Vs) when the applied voltage is changed from +Vs to −⅓Vs, and 0.1 P(−Vs)>P(+⅓Vs) when the applied voltage is changed from −Vs to +⅓Vs.
    Type: Application
    Filed: December 27, 2001
    Publication date: October 31, 2002
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Kazumasa Hasegawa, Eiji Natori, Hiromu Miyazawa, Junichi Karasawa
  • Publication number: 20020155667
    Abstract: The present invention relates to a ferroelectric memory having a matrix-type memory cell array which has an excellent degree of integration, in which the angularity of the ferroelectric layer's hysteresis curve is improved. A ferroelectric memory having both integration and memory characteristics in which the angularity of the ferroelectric layer's hysteresis curve is improved is realized as follows. Namely, a structure is employed in which the memory cell array and the peripheral circuit are in a plane separated from one another, and the ferroelectric layer is made to undergo epitaxial growth on to a Si single crystal via a buffer and the first signal electrodes.
    Type: Application
    Filed: March 22, 2002
    Publication date: October 24, 2002
    Inventors: Takamitsu Higuchi, Setsuya Iwashita, Hiromu Miyazawa, Kazumasa Hasegawa, Eiji Natori
  • Publication number: 20020155666
    Abstract: The present invention relates to a ferroelectric memory having a matrix-type memory cell array which has a superior degree of integration, in which the angularity of the ferroelectric layer's hysteresis curve is improved, the production yield is increased and costs are reduced.
    Type: Application
    Filed: March 22, 2002
    Publication date: October 24, 2002
    Inventors: Takamitsu Higuchi, Setsuya Iwashita, Hiromu Miyazawa, Kazumasa Hasegawa, Eiji Natori
  • Publication number: 20020145903
    Abstract: A ferroelectric memory device includes a memory cell array in which a plurality of memory cells having at least one ferroelectric capacitor are arranged. Three or more values of data (Pr(0), P1(1), and −Pr(2), for example) can be selectively stored in the ferroelectric capacitor by applying voltages having three or more different values for setting three or more polarization states in the ferroelectric capacitor.
    Type: Application
    Filed: December 27, 2001
    Publication date: October 10, 2002
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Kazumasa Hasegawa
  • Patent number: 6455106
    Abstract: A process for the formation of an oxide ceramic thin film, which permits the control of film oxygen content and can give a film reduced in oxygen deficiency. The process is characterized in that the step of forming an amorphous thin film, the step of heating the thin film to crystallize it or the step of heat-treating the crystallized film is conducted in a moisture-containing atmosphere.
    Type: Grant
    Filed: December 28, 1999
    Date of Patent: September 24, 2002
    Assignee: Seiko Epson Corporation
    Inventors: Hong Qiu, Kouji Sumi, Masato Shimada, Tsutomu Nishiwaki, Kazumasa Hasegawa
  • Patent number: 6373461
    Abstract: A first electrode layer 12, a first piezoelectric film layer 13, a second electrode layer 14, a second piezoelectric film layer 15, and a third electrode layer 16 are layered in that order on a substrate 11; these are constrained so as not to expand or contract in a thickness direction and a piezoelectric transducer is constructed thereby.
    Type: Grant
    Filed: January 28, 2000
    Date of Patent: April 16, 2002
    Assignee: Seiko Epson Corporation
    Inventors: Kazumasa Hasegawa, Tatsuya Shimoda
  • Publication number: 20020036934
    Abstract: A ferroelectric memory device of the present invention includes a memory cell array in which memory cells are arranged in a matrix having first signal electrodes, second signal electrodes arranged in a direction intersecting the first signal electrodes, and a ferroelectric layer disposed at least in intersection regions between the first signal electrodes and the second signal electrodes, and a peripheral circuit section for selectively writing information into or reading information from the memory cell. The memory cell array and the peripheral circuit section are formed in different layers. The peripheral circuit section is formed in a region outside the memory cell array.
    Type: Application
    Filed: August 23, 2001
    Publication date: March 28, 2002
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Kazumasa Hasegawa, Eiji Natori, Takao Nishikawa, Koichi Oguchi, Tatsuya Shimoda
  • Publication number: 20020031005
    Abstract: The present invention relates to: a memory cell array which is capable of decreasing the parasitic capacitance of signal electrodes and has ferroelectric layers making up ferroelectric capacitors and having a predetermined pattern; a method of fabricating the memory cell array, and a ferroelectric memory device. In the memory cell array, memory cells formed of ferroelectric capacitors are arranged in a matrix. The ferroelectric capacitors include first signal electrodes, second signal electrodes arranged in a direction intersecting the first signal electrodes, and ferroelectric layers disposed linearly along either the first signal electrodes or the second signal electrodes. Alternatively, the ferroelectric layers may be disposed only in intersection areas of the first and second signal electrodes.
    Type: Application
    Filed: August 20, 2001
    Publication date: March 14, 2002
    Applicant: Seiko Epson Corporation
    Inventors: Eiji Natori, Kazumasa Hasegawa, Koichi Oguchi, Takao Nishikawa, Tatsuya Shimoda
  • Publication number: 20020018357
    Abstract: A ferroelectric memory device includes a memory cell array and a peripheral circuit section. The memory cell array, in which memory cells are arranged in a matrix, includes first signal electrodes, second signal electrodes which are arranged in a direction so as to intersect the first signal electrodes, and a ferroelectric layer disposed at least at intersection regions between the first signal electrodes and the second signal electrodes. The peripheral circuit section includes circuits for selectively allowing information to be written into or read from the memory cells, such as a first driver circuit, a second driver circuit, and a signal detection circuit. The memory cell array and the peripheral circuit section are disposed in different layers so as to be layered. This ferroelectric memory device can significantly increase the degree of integration of the memory cells and decrease the chip area.
    Type: Application
    Filed: July 2, 2001
    Publication date: February 14, 2002
    Applicant: Seiko Epson Corporation
    Inventors: Koichi Oguchi, Eiji Natori, Kazumasa Hasegawa
  • Publication number: 20020017667
    Abstract: A ferroelectric memory according to the present invention includes a passive matrix array in which memory cells formed of ferroelectric capacitors are arranged, and a peripheral circuit for the passive matrix array. The passive matrix array is formed of a passive matrix array microchip, and the peripheral circuit such as a word line driver circuit or a bit line driver circuit is formed on a peripheral circuit substrate, thereby integrating the passive matrix array microchip on the peripheral circuit substrate. Since this allows the passive matrix array and the peripheral circuit therefor to be separately fabricated, the peripheral circuit is not adversely affected when fabricating the passive matrix array, thereby decreasing the degree of limitation in the fabrication process.
    Type: Application
    Filed: June 28, 2001
    Publication date: February 14, 2002
    Applicant: Seiko Epson Corporation
    Inventors: Tatsuya Shimoda, Koichi Oguchi, Eiji Natori, Kazumasa Hasegawa, Atsushi Takakuwa
  • Patent number: 6345424
    Abstract: A production method for forming a liquid spray head. A diaphragm is formed on a first surface of a substrate made of planar oriented (110) monocrystalline silicon. A piezoelectric element is formed by laminating a first electrode, a piezoelectric film and a second electrode arranged on the diaphragm. A liquid chamber is formed by etching so that is extends in one of the <1I2> direction and the <I12> direction at a predetermined position on a second surface of the substrate, which opposes the first surface thereof.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: February 12, 2002
    Assignee: Seiko Epson Corporation
    Inventors: Kazumasa Hasegawa, Masato Shimada, Masayuki Sawada
  • Publication number: 20020011986
    Abstract: A first electrode layer 12, a first piezoelectric film layer 13, a second electrode layer 14, a second piezoelectric film layer 15, and a third electrode layer 16 are layered in that order on a substrate 11; these are constrained so as not to expand or contract in a thickness direction and a piezoelectric transducer is constructed thereby.
    Type: Application
    Filed: October 11, 2001
    Publication date: January 31, 2002
    Inventors: Kazumasa Hasegawa, Tatsuya Shimoda
  • Patent number: 6276781
    Abstract: The liquid jet recording head of this invention is configured such that the upper electrodes on a head substrate and the output terminals of a drive circuit using a thin film transistor are connected so as to face each other. P-channel thin film transistors are used in the analog switches in the drive circuit, and the piezoelectric device drive start timing is made to lag behind the timing with which the analog switches begin conducting.
    Type: Grant
    Filed: September 1, 1998
    Date of Patent: August 21, 2001
    Assignee: Seiko Epson Corporation
    Inventor: Kazumasa Hasegawa
  • Patent number: 5933167
    Abstract: A printer head for ink jet recording is disclosed, comprising a single-crystal silicon substrate pierced with holes, a zirconium oxide layer which is brought into direct contact with the surface of the silicon substrate or a silicon oxide layer on the surface of the silicon substrate so as to cover one end of the holes in the silicon substrate, a lower electrode provided on the zirconium oxide layer, a piezoelectric layer provided on the lower electrode, and an upper electrode provided on the piezoelectric layer. A process for the preparation of the above printer head for ink jet recording is also disclosed. The printer head for ink jet recording can support a piezoelectric substance having a high piezoelectricity, can exhibit a high head drive durability and can be produced in a high yield.
    Type: Grant
    Filed: April 3, 1996
    Date of Patent: August 3, 1999
    Assignee: Seiko Epson Corporation
    Inventors: Masato Shimada, Kazumasa Hasegawa
  • Patent number: 5802686
    Abstract: A printer head for ink jet recording is disclosed, comprising a single-crystal silicon substrate pierced with holes, a zirconium oxide layer which is brought into direct contact with the surface of the silicon substrate or a silicon oxide layer on the surface of the silicon substrate so as to cover one end of the holes in the silicon substrate, a lower electrode provided on the zirconium oxide layer, a piezoelectric layer provided on the lower electrode, and an upper electrode provided on the piezoelectric layer. A process for the preparation of the above printer head for ink jet recording is also disclosed. The printer head for ink jet recording can support a piezoelectric substance having a high piezoelectricity, can exhibit a high head drive durability and can be produced in a high yield.
    Type: Grant
    Filed: May 20, 1997
    Date of Patent: September 8, 1998
    Assignee: Seiko Epson Corporation
    Inventors: Masato Shimada, Kazumasa Hasegawa
  • Patent number: 5719607
    Abstract: A highly reliable liquid jet head having excellent properties, comprising a silicon substrate, a tantalum layer having a thickness of 1,100 angstroms or more formed on the substrate, and a piezoelectric device provided on the tantalum layer, containing a layer of titanium oxide or of an oxide of titanium alloy between the tantalum layer and the electrode, or between the electrode and the piezoelectric film is obtained without suffering the formation of cavities in the silicon dioxide layer or the exfoliation between the electrode an a layer adjacent thereto.
    Type: Grant
    Filed: August 24, 1995
    Date of Patent: February 17, 1998
    Assignee: Seiko Epson Corporation
    Inventors: Kazumasa Hasegawa, Masato Shimada
  • Patent number: 5530465
    Abstract: The present invention relates to a liquid spray head provided with a plurality of liquid spray elements arranged in an array on a substrate. Each element comprises a chamber arranged on the substrate for holding a liquid to be sprayed, a nozzle, a liquid path for communication with the nozzle and the chamber, a diaphragm arranged on the liquid chamber, a piezoelectric element comprising a lower electrode arranged on the diaphragm, a piezoelectric film comprising a lead zirconate titanate film arranged on the lower electrode and an upper electrode arranged on the piezoelectric film. Energy is applied to the piezoelectric element so as to bend the diaphragm for deforming a volume of the liquid chambers to spray the liquid. The liquid chambers have a pitch equal to the pitch of the nozzles, and the following relationships are satisfied:1) 10.ltoreq.W/L.ltoreq.1502) tp.gtoreq.tv3) 0.012.ltoreq.(tp+tv)/L<0.
    Type: Grant
    Filed: December 15, 1993
    Date of Patent: June 25, 1996
    Assignee: Seiko Epson Corporation
    Inventors: Kazumasa Hasegawa, Masato Shimada, Masayuki Sawada
  • Patent number: 4371392
    Abstract: Refining method of molten metal which employs a refining apparatus provided with a tiltable refining vessel, a tuyere formed therein for blowing inert gas and/or flux or further sometimes additive alloy component(s), with the aid of inert gas into the molten metal, and a suitable number of electrodes for heating the molten metal and flux, for the purpose of performing a first refining process of carrying out the heating of the molten metal and the flux with the electrodes and a second refining process of tilting the vessel for blowing into the molten metal insert gas and others from the tuyere, whereby harmful or unnecessary metallic and/or non-metallic impure components can be removed for improving the quality of the article.
    Type: Grant
    Filed: July 20, 1981
    Date of Patent: February 1, 1983
    Assignee: Daido Tokishuko Kabushiki Kaisha
    Inventors: Kazumasa Hasegawa, Minao Ito, Saburo Sugiura, Kiyoichi Yamano, Shizunori Hayakawa
  • Patent number: 4308415
    Abstract: Refining method of molten metal which employs a refining apparatus provided with a tiltable refining vessel, a tuyere formed therein for blowing inert gas and/or flux or further sometimes additive alloy component(s), with the aid of inert gas into the molten metal, and a suitable number of electrodes for heating the molten metal and flux, for the purpose of performing a first refining process of carrying out the heating of the molten metal and the flux with the electrodes and a second refining process of tilting the vessel for blowing into the molten metal inert gas and others from the tuyere, whereby harmful or unnecessary metallic and/or non-metallic impure components can be removed for improving the quality of the article.
    Type: Grant
    Filed: December 5, 1979
    Date of Patent: December 29, 1981
    Assignee: Daido Tokushuko Kabushiki Kaisha
    Inventors: Kazumasa Hasegawa, Minao Ito, Saburo Sugiura, Kiyoichi Yamano, Shizunori Hayakawa