Patents by Inventor Kazumasa Yanagisawa

Kazumasa Yanagisawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190371799
    Abstract: A memory cell includes a memory gate structure, a first select gate structure, and a second select gate structure. In the memory gate structure, a lower memory gate insulating film, a charge storage layer, an upper memory gate insulating film, and a metal memory gate electrode are stacked in this order. The first select gate structure includes a metal first select gate electrode along a first sidewall spacer provided on a sidewall of the memory gate structure. The second select gate structure includes a metal second select gate electrode along a second sidewall spacer provided on another sidewall of the memory gate structure. Thus, the metal memory gate electrode, the metal first select gate electrode, and the metal second select gate electrode can be formed of a same metallic material as a metal logic gate electrode, permitting the memory cell to be formed together with the metal logic gate electrode.
    Type: Application
    Filed: August 14, 2019
    Publication date: December 5, 2019
    Inventors: Shoji YOSHIDA, Fukuo OWADA, Daisuke OKADA, Yasuhiko KAWASHIMA, Shinji YOSHIDA, Kazumasa YANAGISAWA, Yasuhiro TANIGUCHI
  • Patent number: 10482949
    Abstract: A semiconductor device includes a first mode and a second mode different from the first mode, includes a memory circuit including a first switch, a memory array, and a peripheral circuit. A first power source line is electrically coupled with an I/O circuit of the peripheral circuit and is supplied with a first voltage in the first mode. A second power source line is electrically coupled with a memory cell of the memory array, and supplied with a second voltage lower than the first voltage in the second mode.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: November 19, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuichiro Ishii, Atsushi Miyanishi, Kazumasa Yanagisawa
  • Patent number: 10446224
    Abstract: When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: October 15, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Masanao Yamaoka, Kenichi Osada, Kazumasa Yanagisawa
  • Patent number: 10431589
    Abstract: A memory cell includes a memory gate structure, a first select gate structure, and a second select gate structure. In the memory gate structure, a lower memory gate insulating film, a charge storage layer, an upper memory gate insulating film, and a metal memory gate electrode are stacked in this order. The first select gate structure includes a metal first select gate electrode along a first sidewall spacer provided on a sidewall of the memory gate structure. The second select gate structure includes a metal second select gate electrode along a second sidewall spacer provided on another sidewall of the memory gate structure. Thus, the metal memory gate electrode, the metal first select gate electrode, and the metal second select gate electrode can be formed of a same metallic material as a metal logic gate electrode, permitting the memory cell to be formed together with the metal logic gate electrode.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: October 1, 2019
    Assignee: FLOADIA CORPORATION
    Inventors: Shoji Yoshida, Fukuo Owada, Daisuke Okada, Yasuhiko Kawashima, Shinji Yoshida, Kazumasa Yanagisawa, Yasuhiro Taniguchi
  • Publication number: 20190296030
    Abstract: When a memory cell (MC) is downsized by reducing the distance between a drain region (12a) and a source region (12b) on the surface of a fin (S2) with a high impurity concentration inside the fin (S2), the shape of the fin (S2) can be set such that a potential difference between a memory gate electrode (MG) and the fin (S2) is reduced to suppress the occurrence of disturbance. Accordingly, the memory cell (MC) achieves downsizing and suppression of the occurrence of disturbance.
    Type: Application
    Filed: June 7, 2019
    Publication date: September 26, 2019
    Inventors: Daisuke OKADA, Kazumasa YANAGISAWA, Fukuo OWADA, Shoji YOSHIDA, Yasuhiko KAWASHIMA, Shinji YOSHIDA, Yasuhiro TANIGUCHI, Kosuke OKUYAMA
  • Patent number: 10373967
    Abstract: When a memory cell (MC) is downsized by reducing the distance between a drain region (12a) and a source region (12b) on the surface of a fin (S2) with a high impurity concentration inside the fin (S2), the shape of the fin (S2) can be set such that a potential difference between a memory gate electrode (MG) and the fin (S2) is reduced to suppress the occurrence of disturbance. Accordingly, the memory cell (MC) achieves downsizing and suppression of the occurrence of disturbance.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: August 6, 2019
    Assignee: FLOADIA CORPORATION
    Inventors: Daisuke Okada, Kazumasa Yanagisawa, Fukuo Owada, Shoji Yoshida, Yasuhiko Kawashima, Shinji Yoshida, Yasuhiro Taniguchi, Kosuke Okuyama
  • Publication number: 20190172524
    Abstract: A semiconductor device includes a first mode and a second mode different from the first mode, includes a memory circuit including a first switch, a memory array, and a peripheral circuit. A first power source line is electrically coupled with an I/O circuit of the peripheral circuit and is supplied with a first voltage in the first mode. A second power source line is electrically coupled with a memory cell of the memory array, and supplied with a second voltage lower than the first voltage in the second mode.
    Type: Application
    Filed: February 11, 2019
    Publication date: June 6, 2019
    Inventors: Yuichiro ISHII, Atsushi MIYANISHI, Kazumasa YANAGISAWA
  • Patent number: 10224096
    Abstract: A semiconductor device includes: a first power source line for supplying a first voltage; a second power source line for supplying a second voltage; a memory circuit coupled with the first and second power source lines; a first switch which electrically coupling the first power source line with the second power source line and electrically decoupling the first power source line from the second power source line, in response to a control signal; a second switch which electrically coupling the first power source line with the second power source line and electrically decoupling the first power source line from the second power source line, in response to the control signal, wherein a memory circuit includes a memory cell array and a peripheral circuit, wherein a memory cell array includes a plurality of memory cells, the memory cells coupled with the second power source line.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: March 5, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuichiro Ishii, Atsushi Miyanishi, Kazumasa Yanagisawa
  • Publication number: 20180286875
    Abstract: When a memory cell (MC) is downsized by reducing the distance between a drain region (12a) and a source region (12b) on the surface of a fin (S2) with a high impurity concentration inside the fin (S2), the shape of the fin (S2) can be set such that a potential difference between a memory gate electrode (MG) and the fin (S2) is reduced to suppress the occurrence of disturbance. Accordingly, the memory cell (MC) achieves downsizing and suppression of the occurrence of disturbance.
    Type: Application
    Filed: December 7, 2016
    Publication date: October 4, 2018
    Applicant: Floadia Corporation
    Inventors: Daisuke OKADA, Kazumasa YANAGISAWA, Fukuo OWADA, Shoji YOSHIDA, Yasuhiko KAWASHIMA, Shinji YOSHIDA, Yasuhiro TANIGUCHI, Kosuke OKUYAMA
  • Publication number: 20180211965
    Abstract: A memory cell includes a memory gate structure, a first select gate structure, and a second select gate structure. In the memory gate structure, a lower memory gate insulating film, a charge storage layer, an upper memory gate insulating film, and a metal memory gate electrode are stacked in this order. The first select gate structure includes a metal first select gate electrode along a first sidewall spacer provided on a sidewall of the memory gate structure. The second select gate structure includes a metal second select gate electrode along a second sidewall spacer provided on another sidewall of the memory gate structure. Thus, the metal memory gate electrode, the metal first select gate electrode, and the metal second select gate electrode can be formed of a same metallic material as a metal logic gate electrode, permitting the memory cell to be formed together with the metal logic gate electrode.
    Type: Application
    Filed: July 21, 2016
    Publication date: July 26, 2018
    Inventors: Shoji YOSHIDA, Fukuo OWADA, Daisuke OKADA, Yasuhiko KAWASHIMA, Shinji YOSHIDA, Kazumasa YANAGISAWA, Yasuhiro TANIGUCHI
  • Publication number: 20180204612
    Abstract: A semiconductor device includes: a first power source line for supplying a first voltage; a second power source line for supplying a second voltage; a memory circuit coupled with the first and second power source lines; a first switch which electrically coupling the first power source line with the second power source line and electrically decoupling the first power source line from the second power source line, in response to a control signal; a second switch which electrically coupling the first power source line with the second power source line and electrically decoupling the first power source line from the second power source line, in response to the control signal, wherein a memory circuit includes a memory cell array and a peripheral circuit, wherein a memory cell array includes a plurality of memory cells, the memory cells coupled with the second power source line.
    Type: Application
    Filed: March 14, 2018
    Publication date: July 19, 2018
    Inventors: Yuichiro Ishii, Atsushi Miyanishi, Kazumasa Yanagisawa
  • Publication number: 20180158511
    Abstract: When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.
    Type: Application
    Filed: February 2, 2018
    Publication date: June 7, 2018
    Inventors: Masanao YAMAOKA, Kenichi OSADA, Kazumasa YANAGISAWA
  • Patent number: 9959925
    Abstract: A semiconductor device including an active mode and a standby mode as operation modes, includes: a first power source line which accepts the supply of power in the active mode; a second power source line which accepts the supply of power in the active mode and the standby mode; a memory circuit to be coupled with the first and second power source lines; and a first switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The memory circuit includes a memory array to be coupled with the second power source line, a peripheral circuit to be coupled with the first power source line, and a second switch which electrically couples the first power source line with the second power source line.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: May 1, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Yuichiro Ishii, Atsushi Miyanishi, Kazumasa Yanagisawa
  • Patent number: 9922698
    Abstract: A semiconductor integrated circuit device has a memory array including SRAM cells, a plurality of sense amplifiers for reading out data stored in the SRAM cells and a plurality of MOSFETS. The MOSFETs are controlled by a control signal to be in one of an active state or a standby state. Part of the MOSFETs are arranged along one end of the memory array and the other parts of the MOSFETs are arranged along another end of the memory array. The other end of the memory array is opposite to the one end of the memory array. The MOSFETs are controlled by the control signal to be turned ON in the active state and to be turned OFF in the standby mode.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: March 20, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masanao Yamaoka, Kenichi Osada, Kazumasa Yanagisawa
  • Publication number: 20180068712
    Abstract: A semiconductor device including an active mode and a standby mode as operation modes, includes: a first power source line which accepts the supply of power in the active mode; a second power source line which accepts the supply of power in the active mode and the standby mode; a memory circuit to be coupled with the first and second power source lines; and a first switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The memory circuit includes a memory array to be coupled with the second power source line, a peripheral circuit to be coupled with the first power source line, and a second switch which electrically couples the first power source line with the second power source line.
    Type: Application
    Filed: October 31, 2017
    Publication date: March 8, 2018
    Inventors: Yuichiro ISHII, Atsushi Miyanishi, Kazumasa Yanagisawa
  • Patent number: 9837140
    Abstract: A semiconductor device including a first N-type well and a second N-type well includes: a memory circuit to be coupled with first and second power source lines; and a first switch which electrically couples the first power source line with the second power source line and electrically decouples the first power source line from the second power source line. The memory circuit includes a memory array to be coupled with the second power source line, a peripheral circuit to be coupled with the first power source line, and a second switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The first and second switches each include a first PMOS transistor arranged in the first N-type well.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: December 5, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Yuichiro Ishii, Atsushi Miyanishi, Kazumasa Yanagisawa
  • Publication number: 20170103803
    Abstract: A semiconductor device including a first N-type well and a second N-type well includes: a memory circuit to be coupled with first and second power source lines; and a first switch which electrically couples the first power source line with the second power source line and electrically decouples the first power source line from the second power source line. The memory circuit includes a memory array to be coupled with the second power source line, a peripheral circuit to be coupled with the first power source line, and a second switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The first and second switches each include a first PMOS transistor arranged in the first N-type well.
    Type: Application
    Filed: December 22, 2016
    Publication date: April 13, 2017
    Inventors: Yuichiro ISHII, Atsushi MIYANISHI, Kazumasa YANAGISAWA
  • Patent number: 9559693
    Abstract: A semiconductor device includes a first power source line which accepts the supply of power in the active mode, a second power source line which accepts the supply of power in the active mode and the standby mode, a memory circuit to be coupled with the first and second power source lines and a first switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The memory circuit includes a memory array, a peripheral circuit and a second switch. Each of the first and second switches includes a first PMOS transistor and a second PMOS transistor.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: January 31, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Yuichiro Ishii, Atsushi Miyanishi, Kazumasa Yanagisawa
  • Publication number: 20160126953
    Abstract: A semiconductor device includes a first power source line which accepts the supply of power in the active mode, a second power source line which accepts the supply of power in the active mode and the standby mode, a memory circuit to be coupled with the first and second power source lines and a first switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The memory circuit includes a memory array, a peripheral circuit and a second switch. Each of the first and second switches includes a first PMOS transistor and a second PMOS transistor.
    Type: Application
    Filed: September 25, 2015
    Publication date: May 5, 2016
    Inventors: Yuichiro Ishii, Atsushi MIYANISHI, Kazumasa YANAGISAWA
  • Patent number: 9159843
    Abstract: To improve the electric performance and reliability of a semiconductor device. A memory gate electrode of a split gate type nonvolatile memory is a metal gate electrode formed from a stacked film of a metal film 6a and a silicon film 6b over the metal film 6a. In an upper end part of the metal film 6a, a metal oxide portion 17 is formed by oxidation of a part of the metal film 6a. A control gate electrode of the split gate type nonvolatile memory is a metal gate electrode formed from a stacked film of a metal film 4a and the silicon film 4b over the metal film 4a.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: October 13, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Kentaro Saito, Kazumasa Yanagisawa, Yasushi Ishii, Koichi Toba