Patents by Inventor Kazumasa Yanagisawa
Kazumasa Yanagisawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180158511Abstract: When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.Type: ApplicationFiled: February 2, 2018Publication date: June 7, 2018Inventors: Masanao YAMAOKA, Kenichi OSADA, Kazumasa YANAGISAWA
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Patent number: 9959925Abstract: A semiconductor device including an active mode and a standby mode as operation modes, includes: a first power source line which accepts the supply of power in the active mode; a second power source line which accepts the supply of power in the active mode and the standby mode; a memory circuit to be coupled with the first and second power source lines; and a first switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The memory circuit includes a memory array to be coupled with the second power source line, a peripheral circuit to be coupled with the first power source line, and a second switch which electrically couples the first power source line with the second power source line.Type: GrantFiled: October 31, 2017Date of Patent: May 1, 2018Assignee: Renesas Electronics CorporationInventors: Yuichiro Ishii, Atsushi Miyanishi, Kazumasa Yanagisawa
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Patent number: 9922698Abstract: A semiconductor integrated circuit device has a memory array including SRAM cells, a plurality of sense amplifiers for reading out data stored in the SRAM cells and a plurality of MOSFETS. The MOSFETs are controlled by a control signal to be in one of an active state or a standby state. Part of the MOSFETs are arranged along one end of the memory array and the other parts of the MOSFETs are arranged along another end of the memory array. The other end of the memory array is opposite to the one end of the memory array. The MOSFETs are controlled by the control signal to be turned ON in the active state and to be turned OFF in the standby mode.Type: GrantFiled: September 12, 2014Date of Patent: March 20, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Masanao Yamaoka, Kenichi Osada, Kazumasa Yanagisawa
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Publication number: 20180068712Abstract: A semiconductor device including an active mode and a standby mode as operation modes, includes: a first power source line which accepts the supply of power in the active mode; a second power source line which accepts the supply of power in the active mode and the standby mode; a memory circuit to be coupled with the first and second power source lines; and a first switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The memory circuit includes a memory array to be coupled with the second power source line, a peripheral circuit to be coupled with the first power source line, and a second switch which electrically couples the first power source line with the second power source line.Type: ApplicationFiled: October 31, 2017Publication date: March 8, 2018Inventors: Yuichiro ISHII, Atsushi Miyanishi, Kazumasa Yanagisawa
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Patent number: 9837140Abstract: A semiconductor device including a first N-type well and a second N-type well includes: a memory circuit to be coupled with first and second power source lines; and a first switch which electrically couples the first power source line with the second power source line and electrically decouples the first power source line from the second power source line. The memory circuit includes a memory array to be coupled with the second power source line, a peripheral circuit to be coupled with the first power source line, and a second switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The first and second switches each include a first PMOS transistor arranged in the first N-type well.Type: GrantFiled: December 22, 2016Date of Patent: December 5, 2017Assignee: Renesas Electronics CorporationInventors: Yuichiro Ishii, Atsushi Miyanishi, Kazumasa Yanagisawa
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Publication number: 20170103803Abstract: A semiconductor device including a first N-type well and a second N-type well includes: a memory circuit to be coupled with first and second power source lines; and a first switch which electrically couples the first power source line with the second power source line and electrically decouples the first power source line from the second power source line. The memory circuit includes a memory array to be coupled with the second power source line, a peripheral circuit to be coupled with the first power source line, and a second switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The first and second switches each include a first PMOS transistor arranged in the first N-type well.Type: ApplicationFiled: December 22, 2016Publication date: April 13, 2017Inventors: Yuichiro ISHII, Atsushi MIYANISHI, Kazumasa YANAGISAWA
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Patent number: 9559693Abstract: A semiconductor device includes a first power source line which accepts the supply of power in the active mode, a second power source line which accepts the supply of power in the active mode and the standby mode, a memory circuit to be coupled with the first and second power source lines and a first switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The memory circuit includes a memory array, a peripheral circuit and a second switch. Each of the first and second switches includes a first PMOS transistor and a second PMOS transistor.Type: GrantFiled: September 25, 2015Date of Patent: January 31, 2017Assignee: Renesas Electronics CorporationInventors: Yuichiro Ishii, Atsushi Miyanishi, Kazumasa Yanagisawa
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Publication number: 20160126953Abstract: A semiconductor device includes a first power source line which accepts the supply of power in the active mode, a second power source line which accepts the supply of power in the active mode and the standby mode, a memory circuit to be coupled with the first and second power source lines and a first switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The memory circuit includes a memory array, a peripheral circuit and a second switch. Each of the first and second switches includes a first PMOS transistor and a second PMOS transistor.Type: ApplicationFiled: September 25, 2015Publication date: May 5, 2016Inventors: Yuichiro Ishii, Atsushi MIYANISHI, Kazumasa YANAGISAWA
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Patent number: 9159843Abstract: To improve the electric performance and reliability of a semiconductor device. A memory gate electrode of a split gate type nonvolatile memory is a metal gate electrode formed from a stacked film of a metal film 6a and a silicon film 6b over the metal film 6a. In an upper end part of the metal film 6a, a metal oxide portion 17 is formed by oxidation of a part of the metal film 6a. A control gate electrode of the split gate type nonvolatile memory is a metal gate electrode formed from a stacked film of a metal film 4a and the silicon film 4b over the metal film 4a.Type: GrantFiled: May 21, 2012Date of Patent: October 13, 2015Assignee: Renesas Electronics CorporationInventors: Kentaro Saito, Kazumasa Yanagisawa, Yasushi Ishii, Koichi Toba
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Publication number: 20150220095Abstract: A semiconductor integrated circuit includes a plurality of output transistors each controlling the magnitude of an output voltage relative to the magnitude of a load current according to a control value indicated by an impedance control signal applied to a control terminal, a voltage monitor circuit outputting an output voltage monitor value indicating a voltage value of the output voltage, and a control circuit controlling the magnitude of the control value according to the magnitude of an error value between a reference voltage indicating a target value of the output voltage and the output voltage monitor value, and controls based on the control value whether any of such transistors be brought to a conducting state. The control circuit increases a change step of the control value relative to the error value during a predetermined period according to prenotification signals for notifying a change of the load current in advance.Type: ApplicationFiled: April 13, 2015Publication date: August 6, 2015Inventors: Masafumi ONOUCHI, Kazuo OTSUGA, Yasuto IGARASHI, Sadayuki MORITA, Koichiro ISHIBASHI, Kazumasa YANAGISAWA
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Patent number: 9030176Abstract: A semiconductor integrated circuit includes a plurality of output transistors each controlling the magnitude of an output voltage relative to the magnitude of a load current according to a control value indicated by an impedance control signal applied to a control terminal, a voltage monitor circuit outputting an output voltage monitor value indicating a voltage value of the output voltage, and a control circuit controlling the magnitude of the control value according to the magnitude of an error value between a reference voltage indicating a target value of the output voltage and the output voltage monitor value, and controls based on the control value whether any of such transistors be brought to a conducting state. The control circuit increases a change step of the control value relative to the error value during a predetermined period according to prenotification signals for notifying a change of the load current in advance.Type: GrantFiled: November 12, 2012Date of Patent: May 12, 2015Assignee: Renesas Electronics CorporationInventors: Masafumi Onouchi, Kazuo Otsuga, Yasuto Igarashi, Sadayuki Morita, Koichiro Ishibashi, Kazumasa Yanagisawa
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Publication number: 20150049541Abstract: When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.Type: ApplicationFiled: September 12, 2014Publication date: February 19, 2015Inventors: Masanao YAMAOKA, Kenichi OSADA, Kazumasa YANAGISAWA
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Patent number: 8867262Abstract: A semiconductor device includes plural memory cells each having a first inverter and a second inverter, with an input of the first inverter being coupled to an output of the second inverter and an input of the second inverter being coupled to an output of the first inverter. The first and second inverters have drive transistors supplied with a source voltage where the source voltage is raised in response to a level shift of a control signal supplied to a switch of a control circuit. The control circuit further includes a resistance element in parallel with a MOS transistor connected as a diode.Type: GrantFiled: April 10, 2012Date of Patent: October 21, 2014Assignee: Renesas Electronics CorporationInventors: Masanao Yamaoka, Kenichi Osada, Kazumasa Yanagisawa
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Patent number: 8829968Abstract: A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.Type: GrantFiled: September 8, 2009Date of Patent: September 9, 2014Assignee: Renesas Electronics CorporationInventors: Hiroyuki Mizuno, Yusuke Kanno, Kazumasa Yanagisawa, Yoshihiko Yasu, Nobuhiro Oodaira
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Patent number: 8576643Abstract: A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has a maximum variation width of a threshold voltage for memorizing an information set larger than that of the second nonvolatile memory area. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information, and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information.Type: GrantFiled: February 8, 2012Date of Patent: November 5, 2013Assignee: Renesas Electronics CorporationInventors: Yutaka Shinagawa, Takeshi Kataoka, Eiichi Ishikawa, Toshihiro Tanaka, Kazumasa Yanagisawa, Kazufumi Suzukawa
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Publication number: 20120299084Abstract: To improve the electric performance and reliability of a semiconductor device. A memory gate electrode of a split gate type nonvolatile memory is a metal gate electrode formed from a stacked film of a metal film 6a and a silicon film 6b over the metal film 6a. In an upper end part of the metal film 6a, a metal oxide portion 17 is formed by oxidation of a part of the metal film 6a. A control gate electrode of the split gate type nonvolatile memory is a metal gate electrode formed from a stacked film of a metal film 4a and the silicon film 4b over the metal film 4a.Type: ApplicationFiled: May 21, 2012Publication date: November 29, 2012Inventors: Kentaro SAITO, Kazumasa YANAGISAWA, Yasushi ISHII, Koichi TOBA
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Patent number: 8264870Abstract: When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.Type: GrantFiled: September 27, 2010Date of Patent: September 11, 2012Assignee: Renesas Electronics CorporationInventors: Masanao Yamaoka, Kenichi Osada, Kazumasa Yanagisawa
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Publication number: 20120195110Abstract: When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.Type: ApplicationFiled: April 10, 2012Publication date: August 2, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Masanao YAMAOKA, Kenichi OSADA, Kazumasa YANAGISAWA
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Patent number: 8222945Abstract: A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.Type: GrantFiled: October 5, 2011Date of Patent: July 17, 2012Assignee: Renesas Electronics CorporationInventors: Hiroyuki Mizuno, Yusuke Kanno, Kazumasa Yanagisawa, Yoshihiko Yasu, Nobuhiro Oodaira
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Publication number: 20120179953Abstract: A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information, and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information more.Type: ApplicationFiled: February 8, 2012Publication date: July 12, 2012Inventors: Yutaka SHINAGAWA, Takeshi KATAOKA, Eiichi ISHIKAWA, Toshihiro TANAKA, Kazumasa YANAGISAWA, Kazufumi SUZUKAWA