Abstract: A method monitors an air-conditioner having a semi-conductor gas sensor, the method including: determining that a refrigerant leakage has occurred on condition that the detection value is equal to or greater than a first threshold when the fan is in operation; starting operation of the fan as a provisional operation if the detection value is equal to or greater than a second threshold when the fan is not in operation; stopping the provisional operation of the fan; determining that a refrigerant leakage has occurred on condition that the detection value is equal to or greater than a third threshold after stopping the provisional operation of the fan; and taking a predetermined action for outputting alarm information and/or limiting supply of refrigerant to the heat exchanger when a refrigerant leakage is determined to have occurred.

Abstract: A plasma processing apparatus includes a balun having a first unbalanced terminal, a second unbalanced terminal, a first balanced terminal, and a second balanced terminal, a grounded vacuum container, a first electrode electrically connected to the first balanced terminal, a second electrode electrically connected to the second balanced terminal, an impedance matching circuit, a first power supply connected to the balun via the impedance matching circuit, and configured to supply a high frequency to the first electrode via the impedance matching circuit and the balun, a low-pass filter, and a second power supply configured to supply a voltage to the first electrode via the low-pass filter.

Abstract: A memory device is configured as single chip to achieve routing control, bandwidth control, traffic monitoring, buffering, and access control of network functions. The memory device includes a search unit that includes a first memory unit and performs a search operation by searching, from the first memory unit, a piece of data corresponding to an input search key, a statistical information processing unit that includes a second memory unit that stores statistical information including the input search key, with which the piece of data has been successfully searched by the search unit, and an address of the piece of data in the first memory unit, and an arithmetic operation unit that updates the statistical information when the search unit successfully searches the pieces of data corresponding to the input search key.

Abstract: A memory device is configured as single chip to achieve routing control, bandwidth control, traffic monitoring, buffering, and access control of network functions. The memory device includes a search unit that includes a first memory unit and performs a search operation by searching, from the first memory unit, a piece of data corresponding to an input search key, a statistical information processing unit that includes a second memory unit that stores statistical information including the input search key, with which the piece of data has been successfully searched by the search unit, and an address of the piece of data in the first memory unit, and an arithmetic operation unit that updates the statistical information when the search unit successfully searches the pieces of data corresponding to the input search key.

Abstract: A semiconductor device includes a plurality of memory arrays and a plurality of memory array control circuits. Each of the plurality of memory array control circuits includes a read/write control circuit for controlling a read/write operation for the memory array, and a selection circuit for selecting and activating the memory array based on a clock signal and an output signal from the read/write control circuit.

Abstract: Array area and power consumption are reduced in a content addressable memory. A comparator for performing a match determination and a size determination is provided commonly for plural entries each storing data to be retrieved. Each entry includes data storage cells for storing data and mask cells for storing mask bits. The number of mask cells is smaller than that of the data storage cells. Search data is transmitted to the comparator via a search data bus. One of the entries is selected according to a predetermined rule. The comparator decodes the mask bits, generates a mask instruction signal, and performs match comparison and size comparison between the search data and data to be retrieved which is stored in the selected entry.

Abstract: A semiconductor device includes a plurality of memory arrays and a plurality of memory array control circuits. Each of the plurality of memory array control circuits includes a read/write control circuit for controlling a read/write operation for the memory array, and a selection circuit for selecting and activating the memory array based on a clock signal and an output signal from the read/write control circuit.

Abstract: The present invention is directed to reduce array area and power consumption in a content addressable memory. A comparator for performing a match determination and a size determination is provided commonly for plural entries each storing data to be retrieved. Each entry includes data storage cells for storing data and mask cells for storing mask bits. The number of mask cells is smaller than that of the data storage cells. Search data is transmitted to the comparator via a search data bus. One of the entries is selected according to a predetermined rule. The comparator decodes the mask bits, generates a mask instruction signal, and performs match comparison and size comparison between the search data and data to be retrieved which is stored in the selected entry.

Abstract: The present invention is directed to reduce array area and power consumption in a content addressable memory. A comparator for performing a match determination and a size determination is provided commonly for plural entries each storing data to be retrieved. Each entry includes data storage cells for storing data and mask cells for storing mask bits. The number of mask cells is smaller than that of the data storage cells. Search data is transmitted to the comparator via a search data bus. One of the entries is selected according to a predetermined rule. The comparator decodes the mask bits, generates a mask instruction signal, and performs match comparison and size comparison between the search data and data to be retrieved which is stored in the selected entry.

Abstract: The present invention is directed to reduce array area and power consumption in a content addressable memory. A comparator for performing a match determination and a size determination is provided commonly for plural entries each storing data to be retrieved. Each entry includes data storage cells for storing data and mask cells for storing mask bits. The number of mask cells is smaller than that of the data storage cells. Search data is transmitted to the comparator via a search data bus. One of the entries is selected according to a predetermined rule. The comparator decodes the mask bits, generates a mask instruction signal, and performs match comparison and size comparison between the search data and data to be retrieved which is stored in the selected entry.

Abstract: The present invention is directed to reduce array area and power consumption in a content addressable memory. A comparator for performing a match determination and a size determination is provided commonly for plural entries each storing data to be retrieved. Each entry includes data storage cells for storing data and mask cells for storing mask bits. The number of mask cells is smaller than that of the data storage cells. Search data is transmitted to the comparator via a search data bus. One of the entries is selected according to a predetermined rule. The comparator decodes the mask bits, generates a mask instruction signal, and performs match comparison and size comparison between the search data and data to be retrieved which is stored in the selected entry.

Abstract: A storage device is connected to a large-capacity low-speed memory, and divides a packet received via a network into a plurality of segments for storage. The storage device includes a small-capacity high-speed memory. A selector writes the first predetermined number of segments in the packet to the small-capacity high-speed memory, and subsequent segments to the large-capacity low-speed memory. Accordingly, regardless of from what queue a segment is read out in a segment read mode, occurrence of wasteful time in packet transfer can be prevented, and the capacity of the small-capacity high-speed memory can be reduced even when the number of queues increases.

Abstract: A plurality of content-addressable-memory sub-arrays simultaneously performs a parallel comparison between data sequences arranged in a row direction of memory cells and a search data sequence input from outside, and outputs a result of the comparison for each data sequence. A first input pin receives an input of the search data sequence. A second input pin receives an input of a search data sequence arbitrarily designating a content-addressable-memory sub-array. Each of the content-addressable-memory sub-arrays includes an activation control unit that controls activation of the content-addressable-memory sub-arrays based on the search data sequence.

Abstract: The present invention is directed to reduce array area and power consumption in a content addressable memory. A comparator for performing a match determination and a size determination is provided commonly for plural entries each storing data to be retrieved. Each entry includes data storage cells for storing data and mask cells for storing mask bits. The number of mask cells is smaller than that of the data storage cells. Search data is transmitted to the comparator via a search data bus. One of the entries is selected according to a predetermined rule. The comparator decodes the mask bits, generates a mask instruction signal, and performs match comparison and size comparison between the search data and data to be retrieved which is stored in the selected entry.

Abstract: A plurality of content-addressable-memory sub-arrays simultaneously performs a parallel comparison between data sequences arranged in a row direction of memory cells and a search data sequence input from outside, and outputs a result of the comparison for each data sequence. A first input pin receives an input of the search data sequence. A second input pin receives an input of a search data sequence arbitrarily designating a content-addressable-memory sub-array. Each of the content-addressable-memory sub-arrays includes an activation control unit that controls activation of the content-addressable-memory sub-arrays based on the search data sequence.

Abstract: A plurality of content-addressable-memory sub-arrays simultaneously performs a parallel comparison between data sequences arranged in a row direction of memory cells and a search data sequence input from outside, and outputs a result of the comparison for each data sequence. A first input pin receives an input of the search data sequence. A second input pin receives an input of a search data sequence arbitrarily designating a content-addressable-memory sub-array. Each of the content-addressable-memory sub-arrays includes an activation control unit that controls activation of the content-addressable-memory sub-arrays based on the search data sequence.

Abstract: A TCAM (ternary content addressable memory) cell array is provided with a search input node into which one bit of search data is inputted, a plurality of data input nodes into which a bit corresponding to one bit of search data is inputted, and a plurality of memory cells arranged in rows and columns. Each of the plurality of memory cells further includes a first cell storing one bit of said storage data, and a logical operation cell determining whether or not said search data and storage data match. A gate of a transistor forming each of a plurality of memory cells extends along the direction of said rows. Each of a plurality of wells in the region where the memory array is formed is formed so as to continue to a corresponding well of an adjacent memory cell in the direction of said columns.

Abstract: A search payload data shift part has n latch parts LT1 to LTn (n?2), each of which can store 1-byte latch data, and obtains search payload data having an n-byte length, while shifting payload data inputted from an input terminal, in synchronization with a clock provided from the exterior. Data related to the search payload data is given to a CAM array, as search object data. When the search object data matches entry data of the CAM array, a hit signal ‘hit’ indicating a match is outputted from the CAM array.

Abstract: A search payload data shift part has n latch parts LT1 to LTn (n?2), each of which can store 1-byte latch data, and obtains search payload data having an n-byte length, while shifting payload data inputted from an input terminal, in synchronization with a clock provided from the exterior. Data related to the search payload data is given to a CAM array, as search object data. When the search object data matches entry data of the CAM array, a hit signal ‘hit’ indicating a match is outputted from the CAM array.

Abstract: A TCAM (ternary content addressable memory) cell array is provided with a search input node into which one bit of search data is inputted, a plurality of data input nodes into which a bit corresponding to one bit of search data is inputted, and a plurality of memory cells arranged in rows and columns. Each of the plurality of memory cells further includes a first cell storing one bit of said storage data, and a logical operation cell determining whether or not said search data and storage data match. A gate of a transistor forming each of a plurality of memory cells extends along the direction of said rows. Each of a plurality of wells in the region where the memory array is formed is formed so as to continue to a corresponding well of an adjacent memory cell in the direction of said columns.