Abstract: A plurality of content-addressable-memory sub-arrays simultaneously performs a parallel comparison between data sequences arranged in a row direction of memory cells and a search data sequence input from outside, and outputs a result of the comparison for each data sequence. A first input pin receives an input of the search data sequence. A second input pin receives an input of a search data sequence arbitrarily designating a content-addressable-memory sub-array. Each of the content-addressable-memory sub-arrays includes an activation control unit that controls activation of the content-addressable-memory sub-arrays based on the search data sequence.

Abstract: The present invention concerns an ingress noise control system and an ingress noise blocking device which are used in a cable system to suppress ingress noise. In the cable system providing two-way communication using different frequency bands for transmission of upstream and downstream signals, the ingress noise control system includes, within a distribution unit, a two-way amplification unit, etc. provided in an upstream signal transmission path, a synchronous detection controller 6 for synchronously detecting the upstream signal transmitted from terminal equipment and separated by a low-pass filter 4 in a second separation filter 2, a gate switch circuit 5 which is turned on by the synchronous detection controller 6 to pass the upstream signal only when the upstream signal is synchronously detected, and an indicator 7 for indicating the on/off state of the gate switch circuit 5.

Abstract: A search payload data shift part has n latch parts LT1 to LTn (n?2), each of which can store 1-byte latch data, and obtains search payload data having an n-byte length, while shifting payload data inputted from an input terminal, in synchronization with a clock provided from the exterior. Data related to the search payload data is given to a CAM array, as search object data. When the search object data matches entry data of the CAM array, a hit signal ‘hit’ indicating a match is outputted from the CAM array.

Abstract: A semiconductor memory can reduce its power consumption by decreasing the activation frequency of search lines during search operation. It includes a CAM cell block for storing memory data expressing each combination of digital values stored in four memory cells in terms of a 2-bit digital value; search lines on which a digital value to be matched with a digital value stored in the memory cells is placed; a search data setting section for placing individual 1-bit digital values on the search lines connected to the memory cells to set the search data expressing a 4-bit combination of digital values in terms of the 2-bit digital value; transistors for deciding match/mismatch between the memory data and search data; and the match line 3 for outputting the decision result.

Abstract: A semiconductor memory can reduce its power consumption by decreasing the activation frequency of search lines during search operation. It includes a CAM cell block for storing memory data expressing each combination of digital values stored in four memory cells in terms of a 2-bit digital value; search lines on which a digital value to be matched with a digital value stored in the memory cells is placed; a search data setting section for placing individual 1-bit digital values on the search lines connected to the memory cells to set the search data expressing a 4-bit combination of digital values in terms of the 2-bit digital value; transistors for deciding match/mismatch between the memory data and search data; and the match line 3 for outputting the decision result.

Abstract: A content addressable memory (CAM) cell array includes a first-stage memory cell array and a second-stage memory cell array. Only when data on search output lines (match lines) connected to the first-stage memory cell array are coincident, the second-stage memory cell array performs search operation. Therefore, power consumption of the CAM cell array can be reduced.

Abstract: A content addressable memory (CAM) cell array includes a first-stage memory cell array and a second-stage memory cell array. Only when data on search output lines (match lines) connected to the first-stage memory cell array are coincident, the second-stage memory cell array performs search operation. Therefore, power consumption of the CAM cell array can be reduced.

Abstract: A central row-related control circuit transmits an internal row address signal to each memory sub block in banks of memory mats asynchronously with an external clock signal, and latches a block selection signal for specifying a memory sub block synchronously with an internal clock signal for one clock cycle period for transmission to each memory sub block. A spare determination circuit performs spare determination asynchronously with the clock signal. A semiconductor memory device easily adaptable to bank expansion without increase of the chip area and capable of implementing a high speed access can be provided.

Abstract: A semiconductor integrated circuit device latches externally applied signals received through input/output pads at registers. Signals output from registers are applied to an internal circuit through a switching circuit. Switching circuit is controlled by a signal MIRROR/EN to invert mirror-symmetrically the relation of the signals applied to the internal circuit and the input/output pads.

Abstract: A DRAM includes a data transfer pipeline register group between a dynamic memory cell array and a static memory cell array, a first unidirectional read bus and a first unidirectional write bus connected between a data transfer bus group and the data transfer pipeline register group, and a second unidirectional write bus and a second unidirectional read bus connected between the data transfer pipeline register group and the static memory cell array. The operating frequency of the second unidirectional write bus and the second unidirectional read bus is N times the operating frequency of the first unidirectional read bus and the first unidirectional write bus. The number of lines of the second unidirectional write bus and the second unidirectional read bus is 1/N time the number of lines of the first unidirectional read bus and the first unidirectional write bus. The dynamic memory cell array is further divided into a hierarchical manner of main banks and subbanks.

Abstract: A frame buffer memory includes, on a semiconductor substrate: a DRAM array in which image information including frame information and window information are stored; two serial access memories for serially outputting the image information read from DRAM array by interleave method; a look-up table for outputting a selection signal in accordance with window information input; and a multiplexer for selectively outputting frame information input in accordance with said selection signal.

Abstract: A DRAM includes a data transfer pipeline register group between a dynamic memory cell array and a static memory cell array, a first unidirectional read bus and a first unidirectional write bus connected between a data transfer bus group and the data transfer pipeline register group, and a second unidirectional write bus and a second unidirectional read bus connected between the data transfer pipeline register group and the static memory cell array. The operating frequency of the second unidirectional write bus and the second unidirectional read bus is N times the operating frequency of the first unidirectional read bus and the first unidirectional write bus. The number of lines of the second unidirectional write bus and the second unidirectional read bus is 1/N time the number of lines of the first unidirectional read bus and the first unidirectional write bus. The dynamic memory cell array is further divided into a hierarchical manner of main banks and subbanks.

Abstract: Two frame buffer memories are used. Depth coordinates are stored in a data bank memory of the first frame buffer memory. A comparing unit makes comparison between the depth coordinate of an image data currently displayed and the newly input depth coordinate, and thereby outputs a comparison result signal from a comparison result signal output terminal. In the second frame buffer memory, color data is stored in a data bank memory, and the comparison result signal sent from the first frame buffer memory is input via a comparison result signal input terminal. An image processing unit performs blending processing on the color data in response to the comparison result signal, and rewrites the color data.

Abstract: A semiconductor memory device having flash write mode and initialized mode functions includes a flash write signal generation circuit for generating flash write signals FW and /FW, and a plurality of switching circuits 30 each provided corresponding to one row in a memory cell arrays MA. The switching circuit 30 applies fixed data "0" or "1" to a memory cell connected to one row selected by a row decoder 10, in response to the flash write signal FW or /FW. Because it is not necessary to activate a column decoder when the flash write or the initialized mode operation is conducted, writing speed can be increased while power consumption can be reduced.

Abstract: A plurality of transfer bit lines each extend longitudinally across a memory array block. Transfer switch circuits are disposed between the transfer bit lines and a serial register. Transfer switch circuits are disposed between the transfer bit lines and a shared sense amplifier circuit. The transfer switch circuits are controlled by internal transfer signals, respectively. Transfer switch circuits are controlled by internal transfer signals, respectively.

Abstract: A multiport memory device includes first and second memory cell arrays divided by a shared sense amplifier circuit, a first serial data register capable of transferring data with a row in the first memory array through a first data bus, a second serial data register capable of transferring data with a row in the second memory array through a second data bus. The multiport memory device activates both the first and second data bus for transferring data of a row in the first or second memory array both to the first and second serial data registers in the same data transfer cycle in response to a dual read transfer instructions.

Abstract: A color data transferring circuit, a color data storing circuit, and a block selecting circuit 1020 are provided separately from an input/output buffer circuit, in order to transmit data stored in a color register to a memory cell block. In a block write mode, data applied to a data input/output terminal is stored in the color data storing circuit through color register and the color data transferring circuit. One block selecting gate is selected in response to a block selecting signal from a block decoder, and data stored in each storage element in the color data storing circuit is transmitted to a corresponding memory cell block. Input/output buffer circuit performs normal data writing only through a sense amplifier +I/O block. A semiconductor memory device capable of easily extending the number of bits of block write with a simple circuit configuration is implemented.

Abstract: A semiconductor memory device capable of internally generating a dummy cycle includes circuits for generating dummy cycle designation signals in response to at least one of predetermined external control signdlsircuits for generating a dummy cycle signal predetermined times in response to the output signal of such circuits. The dummy cycle signal drives a desired internal circuit. The internal and automatic generation of a dummy cycle signal allows a circuit in addition to an RAS related circuit to execute a dummy cycle. As a result, a semiconductor memory device having multi-function is allowed to reliably initialize a desired internal circuit without designing complicated timing and providing additional pin terminals.

Abstract: A write enable buffer circuit for generating an internal write designating signal includes a gate circuit for inhibiting generation of the signal in response to an internal output designating signal which attains a settled state prior to a data outputting operation by a data outputting buffer. In data reading, the gate circuit forbids generation of an internal write designating signal to certainly hold the internal write designating signal in a disable state even if a noise is generated in data output. Thus, it is prevented that an internal write designating signal is erroneously generated due to noise in data output to bring data output buffer into an output high impedance state, and also the data input buffer is certainly maintained at an inactive state in data output.

Abstract: The semiconductor memory device includes a serial memory cell array and an input-output circuit. The input-output circuit includes first and second latch circuits, first and second transfer circuits and an output circuit. The first transfer circuit transfers the information read from the serial memory cell array to the first latch circuit. The second transfer circuit transfers the information from the first latch circuit 103 to the second latch circuit 105. The output circuit externally supplies as output the information held in the second latch circuit. A clock generator supplies a clock signal to the first and the second transfer circuits and the output circuit so that the output operation by the output circuit may be effected, and then the transfer operation by the first transfer circuit may be effected after the transfer by the second transfer circuit has been effected.