Patents by Inventor Kazunari Ishimaru
Kazunari Ishimaru has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7772692Abstract: A semiconductor device comprises: a semiconductor element; a mounting substrate with the semiconductor element mounted thereon; a first high thermal conductivity member formed on a surface of the mounting substrate; and a first cooling member thermally connected to at least a part of the first high thermal conductivity member. The first high thermal conductivity member is thermally connected to the semiconductor element, and the first high thermal conductivity member has an outer edge which is located outside an outer edge of the semiconductor element.Type: GrantFiled: August 27, 2007Date of Patent: August 10, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Tomonao Takamatsu, Hideo Aoki, Kazunari Ishimaru
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Patent number: 7723171Abstract: According to the present invention, there is provided a semiconductor device fabrication method, comprising: depositing a mask material on a semiconductor substrate; patterning the mask material and forming a trench in a surface portion of the semiconductor substrate by etching, thereby forming a first projection in a first region, and a second projection wider than the first projection in a second region; burying a device isolation insulating film in the trench; etching away a predetermined amount of the device isolation insulating film formed in the first region; etching away the mask material formed in the second region; forming a first gate insulating film on a pair of opposing side surfaces of the first projection, and a second gate insulating film on an upper surface of the second projection; depositing a first gate electrode material on the device isolation insulating film, mask material, and second gate insulating film; planarizing the first gate electrode material by using as stoppers the mask materiType: GrantFiled: April 2, 2008Date of Patent: May 25, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Atsushi Yagishita, Akio Kaneko, Kazunari Ishimaru
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Patent number: 7687368Abstract: A semiconductor device manufacturing method is disclosed. The method is to form a second semiconductor layer which has less susceptibility to adopting insulative characteristics than a first semiconductor layer on the first semiconductor layer. Then, grooves which expose portions of the second and first semiconductor layers are formed to extend from the upper surface of the second semiconductor layer into the first semiconductor layer. Next, portions of the first and second semiconductor layers which are exposed to the grooves are changed into an insulator form to fill the grooves with the insulator-form portions of the first semiconductor layer.Type: GrantFiled: March 25, 2005Date of Patent: March 30, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Hirohisa Kawasaki, Kazunari Ishimaru, Kunihiro Kasai, Yasunori Okayama
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Patent number: 7541245Abstract: A semiconductor device includes a semiconductor substrate, an insulating film projected on a surface of the semiconductor substrate, a semiconductor film provided on a side surface of the insulating film, and MIS transistor formed in the semiconductor film, the MIS transistor having source, gate and drain region. The semiconductor device further includes a gate electrode provided on the gate region of the MIS transistor, the length of the gate electrode being larger than the thickness of the semiconductor film.Type: GrantFiled: December 12, 2006Date of Patent: June 2, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Hirohisa Kawasaki, Kazunari Ishimaru
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Patent number: 7468923Abstract: There is provided a semiconductor integrated circuit including a logic circuit and a writing circuit configured to receive a writing data outputted from the logic circuit, invert the writing data to generate an inverted data, compare the writing data with the inverted data and output the held writing data if the writing data is different from the inverted data.Type: GrantFiled: December 20, 2006Date of Patent: December 23, 2008Assignee: Kabushiki Kaisha ToshibaInventor: Kazunari Ishimaru
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Patent number: 7432542Abstract: A semiconductor device includes a first semiconductor layer, and a first insulated-gate field-effect transistor of a first conductivity type that is provided in a major surface region of the first semiconductor layer. The semiconductor device further includes an electrostrictive layer that is provided on a back surface of the first semiconductor layer and applies a first stress along a channel length to a channel region of the first insulated-gate field-effect transistor when the first insulated-gate field-effect transistor is operated.Type: GrantFiled: May 31, 2006Date of Patent: October 7, 2008Assignee: Kabushiki Kaisha ToshibaInventor: Kazunari Ishimaru
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Publication number: 20080220582Abstract: According to the present invention, there is provided a semiconductor device fabrication method, comprising: depositing a mask material on a semiconductor substrate; patterning the mask material and forming a trench in a surface portion of the semiconductor substrate by etching, thereby forming a first projection in a first region, and a second projection wider than the first projection in a second region; burying a device isolation insulating film in the trench; etching away a predetermined amount of the device isolation insulating film formed in the first region; etching away the mask material formed in the second region; forming a first gate insulating film on a pair of opposing side surfaces of the first projection, and a second gate insulating film on an upper surface of the second projection; depositing a first gate electrode material on the device isolation insulating film, mask material, and second gate insulating film; planarizing the first gate electrode material by using as stoppers the mask matType: ApplicationFiled: April 2, 2008Publication date: September 11, 2008Inventors: Atsushi Yagishita, Akio Kaneko, Kazunari Ishimaru
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Patent number: 7371644Abstract: According to the present invention, there is provided a semiconductor device fabrication method, comprising: depositing a mask material on a semiconductor substrate; patterning the mask material and forming a trench in a surface portion of the semiconductor substrate by etching, thereby forming a first projection in a first region, and a second projection wider than the first projection in a second region; burying a device isolation insulating film in the trench; etching away a predetermined amount of the device isolation insulating film formed in the first region; etching away the mask material formed in the second region; forming a first gate insulating film on a pair of opposing side surfaces of the first projection, and a second gate insulating film on an upper surface of the second projection; depositing a first gate electrode material on the device isolation insulating film, mask material, and second gate insulating film; planarizing the first gate electrode material by using as stoppers the mask matType: GrantFiled: April 17, 2006Date of Patent: May 13, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Atsushi Yagishita, Akio Kaneko, Kazunari Ishimaru
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Publication number: 20080067673Abstract: A semiconductor device comprises: a semiconductor element; a mounting substrate with the semiconductor element mounted thereon; a first high thermal conductivity member formed on a surface of the mounting substrate; and a first cooling member thermally connected to at least a part of the first high thermal conductivity member. The first high thermal conductivity member is thermally connected to the semiconductor element, and the first high thermal conductivity member has an outer edge which is located outside an outer edge of the semiconductor element.Type: ApplicationFiled: August 27, 2007Publication date: March 20, 2008Inventors: Tomonao Takamatsu, Hideo Aoki, Kazunari Ishimaru
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Publication number: 20070147138Abstract: There is provided a semiconductor integrated circuit including a logic circuit and a writing circuit configured to receive a writing data outputted from the logic circuit, invert the writing data to generate an inverted data, compare the writing data with the inverted data and output the held writing data if the writing data is different from the inverted data.Type: ApplicationFiled: December 20, 2006Publication date: June 28, 2007Applicant: Kabushiki Kaisha ToshibaInventor: Kazunari ISHIMARU
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Patent number: 7235469Abstract: A semiconductor device suitable for the miniaturization and comprising properly controlled Si/SiGe gate electrode comprises an insulator formed on a semiconductor substrate, a first gate electrode formed on the insulator and including silicon-germanium, wherein a germanium concentration is higher near an interface to the insulator and lower in a surface side opposite to the insulator, and a second gate electrode formed on the insulator and including silicon-germanium, wherein a germanium concentration is substantially uniform and an n-type dopant of a concentration of above 6×1020 atoms/cm3 is contained.Type: GrantFiled: November 29, 2004Date of Patent: June 26, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Yasunori Okayama, Kiyotaka Miyano, Kazunari Ishimaru
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Publication number: 20070090468Abstract: A semiconductor device includes a semiconductor substrate, an insulating film projected on a surface of the semiconductor substrate, a semiconductor film provided on a side surface of the insulating film, and MIS transistor formed in the semiconductor film, the MIS transistor having source, gate and drain region. The semiconductor device further includes a gate electrode provided on the gate region of the MIS transistor, the length of the gate electrode being larger than the thickness of the semiconductor film.Type: ApplicationFiled: December 12, 2006Publication date: April 26, 2007Applicant: Kabushiki Kaisha ToshibaInventors: Hirohisa Kawasaki, Kazunari Ishimaru
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Patent number: 7164175Abstract: A semiconductor device includes a semiconductor substrate, an insulating film projected on a surface of the semiconductor substrate, a semiconductor film provided on a side surface of the insulating film, and MIS transistor formed in the semiconductor film, the MIS transistor having source, gate and drain region. The semiconductor device further includes a gate electrode provided on the gate region of the MIS transistor, the length of the gate electrode being larger than the thickness of the semiconductor film.Type: GrantFiled: April 28, 2004Date of Patent: January 16, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Hirohisa Kawasaki, Kazunari Ishimaru
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Publication number: 20070007566Abstract: A semiconductor device having a semiconductor substrate, a SRAM area formed in the semiconductor substrate, the SRAM area having first transistors, the first transistor having a metallic compound film formed on each of a source and a drain regions of the first transistor, and a logic circuit area formed in the semiconductor substrate, the logic circuit area having a second transistor, the second transistor having a metallic compound film on each of a source and a drain regions of the second transistor. The thickness of the metallic compound film of the second transistor is thicker than thickness of the metallic compound film of the first transistor.Type: ApplicationFiled: July 6, 2006Publication date: January 11, 2007Inventor: Kazunari Ishimaru
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Publication number: 20060278903Abstract: A semiconductor device includes a first semiconductor layer, and a first insulated-gate field-effect transistor of a first conductivity type that is provided in a major surface region of the first semiconductor layer. The semiconductor device further includes an electrostrictive layer that is provided on a back surface of the first semiconductor layer and applies a first stress along a channel length to a channel region of the first insulated-gate field-effect transistor when the first insulated-gate field-effect transistor is operated.Type: ApplicationFiled: May 31, 2006Publication date: December 14, 2006Inventor: Kazunari Ishimaru
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Publication number: 20060275988Abstract: According to the present invention, there is provided a semiconductor device fabrication method, comprising: depositing a mask material on a semiconductor substrate; patterning the mask material and forming a trench in a surface portion of the semiconductor substrate by etching, thereby forming a first projection in a first region, and a second projection wider than the first projection in a second region; burying a device isolation insulating film in the trench; etching away a predetermined amount of the device isolation insulating film formed in the first region; etching away the mask material formed in the second region; forming a first gate insulating film on a pair of opposing side surfaces of the first projection, and a second gate insulating film on an upper surface of the second projection; depositing a first gate electrode material on the device isolation insulating film, mask material, and second gate insulating film; planarizing the first gate electrode material by using as stoppers the mask materiType: ApplicationFiled: April 17, 2006Publication date: December 7, 2006Inventors: Atsushi Yagishita, Akio Kaneko, Kazunari Ishimaru
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Patent number: 7129550Abstract: A semiconductor layer in which a primary part of a FinFET is formed, i.e., a fin has a shape which is long in a direction x and short in a direction y. A width of the fin in the direction y changes on three stages. First, in a channel area between gate electrodes each having a gate length Lg, the width of the fin in the direction y is Wch. Further, the width of the fin in the direction y in a source/drain extension area adjacent to the channel area in the direction x is Wext (>Wch). Furthermore, the width of the fin in the direction y in a source/drain area adjacent to the source/drain extension area in the direction x is Wsd (>Wext).Type: GrantFiled: February 9, 2004Date of Patent: October 31, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Makoto Fujiwara, Kazunari Ishimaru, Akira Hokazono
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Publication number: 20060237788Abstract: A semiconductor device has a semiconductor substrate, a first MOSFET which has a first gate insulating film made of a high dielectric material formed above the semiconductor substrate and a first gate electrode formed above the first gate insulating film, an insulating film which is formed directly on sidewalls of the first gate electrode and made of a material having dielectric constant smaller than that of the first gate insulating film, and a second MOSFET which has a second gate insulating film made of a material having dielectric constant smaller than that of the first gate insulating film formed above the semiconductor substrate and a second gate electrode formed above the second gate insulating film, wherein the first gate electrode is formed of a first silicide or a first metal; and the second gate electrode is formed including a film made of at least one of polysilicon, amorphous silicon, polysilicon germanium and amorphous silicon germanium.Type: ApplicationFiled: March 1, 2006Publication date: October 26, 2006Inventor: Kazunari Ishimaru
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Publication number: 20060170047Abstract: A semiconductor device according to an embodiment of the present invention comprises a semiconductor substrate; and a plurality of MOSFETs which are formed on the semiconductor substrate, are the same conductivity type, and have gate insulating films of the same insulating material, with each gate insulating film having any one of a plurality of different thicknesses, and wherein a gate electrode of the MOSFET having a first gate insulating film of a small thickness, consisting substantially of silicide, and a gate electrode of a MOSFET having a second gate insulating film of a thickness larger than that of the first gate insulating film has a structure consisting of polycrystalline silicon, amorphous silicon or silicon-germanium and silicide formed on the polycrystalline silicon, amorphous silicon or germanium silicon.Type: ApplicationFiled: December 9, 2005Publication date: August 3, 2006Inventor: Kazunari Ishimaru
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Publication number: 20060166456Abstract: A semiconductor layer in which a primary part of a FinFET is formed, i.e., a fin has a shape which is long in a direction x and short in a direction y. A width of the fin in the direction y changes on three stages. First, in a channel area between gate electrodes each having a gate length Lg, the width of the fin in the direction y is Wch. Further, the width of the fin in the direction y in a source/drain extension area adjacent to the channel area in the direction x is Wext (>Wch). Furthermore, the width of the fin in the direction y in a source/drain area adjacent to the source/drain extension area in the direction x is Wsd (>Wext).Type: ApplicationFiled: March 25, 2006Publication date: July 27, 2006Inventors: Makoto Fujiwara, Kazunari Ishimaru, Akira Hokazono