Patents by Inventor Kazunari Ishimaru

Kazunari Ishimaru has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10593486
    Abstract: An electrolytic capacitor includes a capacitor element, a solid electrolyte layer, an electrolyte solution. The capacitor element has an anode foil with a dielectric layer, and a cathode foil. The solid electrolyte layer is provided between the anode foil and the cathode foil. And the capacitor element is impregnated with the electrolyte solution. The cathode foil includes a covering layer that contains at least one metal selected from titanium and nickel or a compound of the at least one metal. And the solid electrolyte layer contains a conductive polymer, a polymer dopant, and a base component.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: March 17, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Tatsuji Aoyama, Kazuhiro Takatani, Kazunari Imamoto, Yoshiaki Ishimaru
  • Publication number: 20200079794
    Abstract: An electrolytic capacitor includes a capacitor element, a solid electrolyte layer, and a liquid substance. The capacitor element includes an anode foil with a dielectric layer, and a cathode foil. The solid electrolyte layer is provided between the anode foil and the cathode foil. The capacitor element is impregnated with the liquid substance that includes a solvent and a solute. The solute contains at least one selected from the group consisting of an acid component, a nitro compound, and a phenol compound. The cathode foil includes a covering layer that contains at least one selected from the group consisting of titanium, nickel, a compound including titanium, and a compound including nickel. And the solid electrolyte layer contains a conductive polymer and a base component.
    Type: Application
    Filed: November 12, 2019
    Publication date: March 12, 2020
    Inventors: Tatsuji AOYAMA, Kazuhiro TAKATANI, Kazunari IMAMOTO, Yoshiaki ISHIMARU
  • Publication number: 20190304704
    Abstract: An electrolytic capacitor includes an anode body including a dielectric layer, a cathode body, and a conductive polymer layer and a liquid component that are disposed between the anode body and the cathode body. The cathode body includes a base material part having an outer surface that is roughened surface and has a pore opened at the outer surface, and an inorganic conductive layer covering at least a part of the outer surface. The base material part includes a first coating layer disposed along at least a part of inner wall of the pore. The first coating layer contains phosphorus.
    Type: Application
    Filed: March 20, 2019
    Publication date: October 3, 2019
    Inventors: YOSHIAKI ISHIMARU, KAZUNARI IMAMOTO, TATSUJI AOYAMA
  • Patent number: 7772692
    Abstract: A semiconductor device comprises: a semiconductor element; a mounting substrate with the semiconductor element mounted thereon; a first high thermal conductivity member formed on a surface of the mounting substrate; and a first cooling member thermally connected to at least a part of the first high thermal conductivity member. The first high thermal conductivity member is thermally connected to the semiconductor element, and the first high thermal conductivity member has an outer edge which is located outside an outer edge of the semiconductor element.
    Type: Grant
    Filed: August 27, 2007
    Date of Patent: August 10, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomonao Takamatsu, Hideo Aoki, Kazunari Ishimaru
  • Patent number: 7723171
    Abstract: According to the present invention, there is provided a semiconductor device fabrication method, comprising: depositing a mask material on a semiconductor substrate; patterning the mask material and forming a trench in a surface portion of the semiconductor substrate by etching, thereby forming a first projection in a first region, and a second projection wider than the first projection in a second region; burying a device isolation insulating film in the trench; etching away a predetermined amount of the device isolation insulating film formed in the first region; etching away the mask material formed in the second region; forming a first gate insulating film on a pair of opposing side surfaces of the first projection, and a second gate insulating film on an upper surface of the second projection; depositing a first gate electrode material on the device isolation insulating film, mask material, and second gate insulating film; planarizing the first gate electrode material by using as stoppers the mask materi
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: May 25, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Yagishita, Akio Kaneko, Kazunari Ishimaru
  • Patent number: 7687368
    Abstract: A semiconductor device manufacturing method is disclosed. The method is to form a second semiconductor layer which has less susceptibility to adopting insulative characteristics than a first semiconductor layer on the first semiconductor layer. Then, grooves which expose portions of the second and first semiconductor layers are formed to extend from the upper surface of the second semiconductor layer into the first semiconductor layer. Next, portions of the first and second semiconductor layers which are exposed to the grooves are changed into an insulator form to fill the grooves with the insulator-form portions of the first semiconductor layer.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: March 30, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirohisa Kawasaki, Kazunari Ishimaru, Kunihiro Kasai, Yasunori Okayama
  • Patent number: 7541245
    Abstract: A semiconductor device includes a semiconductor substrate, an insulating film projected on a surface of the semiconductor substrate, a semiconductor film provided on a side surface of the insulating film, and MIS transistor formed in the semiconductor film, the MIS transistor having source, gate and drain region. The semiconductor device further includes a gate electrode provided on the gate region of the MIS transistor, the length of the gate electrode being larger than the thickness of the semiconductor film.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: June 2, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirohisa Kawasaki, Kazunari Ishimaru
  • Patent number: 7468923
    Abstract: There is provided a semiconductor integrated circuit including a logic circuit and a writing circuit configured to receive a writing data outputted from the logic circuit, invert the writing data to generate an inverted data, compare the writing data with the inverted data and output the held writing data if the writing data is different from the inverted data.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: December 23, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazunari Ishimaru
  • Patent number: 7432542
    Abstract: A semiconductor device includes a first semiconductor layer, and a first insulated-gate field-effect transistor of a first conductivity type that is provided in a major surface region of the first semiconductor layer. The semiconductor device further includes an electrostrictive layer that is provided on a back surface of the first semiconductor layer and applies a first stress along a channel length to a channel region of the first insulated-gate field-effect transistor when the first insulated-gate field-effect transistor is operated.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: October 7, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazunari Ishimaru
  • Publication number: 20080220582
    Abstract: According to the present invention, there is provided a semiconductor device fabrication method, comprising: depositing a mask material on a semiconductor substrate; patterning the mask material and forming a trench in a surface portion of the semiconductor substrate by etching, thereby forming a first projection in a first region, and a second projection wider than the first projection in a second region; burying a device isolation insulating film in the trench; etching away a predetermined amount of the device isolation insulating film formed in the first region; etching away the mask material formed in the second region; forming a first gate insulating film on a pair of opposing side surfaces of the first projection, and a second gate insulating film on an upper surface of the second projection; depositing a first gate electrode material on the device isolation insulating film, mask material, and second gate insulating film; planarizing the first gate electrode material by using as stoppers the mask mat
    Type: Application
    Filed: April 2, 2008
    Publication date: September 11, 2008
    Inventors: Atsushi Yagishita, Akio Kaneko, Kazunari Ishimaru
  • Patent number: 7371644
    Abstract: According to the present invention, there is provided a semiconductor device fabrication method, comprising: depositing a mask material on a semiconductor substrate; patterning the mask material and forming a trench in a surface portion of the semiconductor substrate by etching, thereby forming a first projection in a first region, and a second projection wider than the first projection in a second region; burying a device isolation insulating film in the trench; etching away a predetermined amount of the device isolation insulating film formed in the first region; etching away the mask material formed in the second region; forming a first gate insulating film on a pair of opposing side surfaces of the first projection, and a second gate insulating film on an upper surface of the second projection; depositing a first gate electrode material on the device isolation insulating film, mask material, and second gate insulating film; planarizing the first gate electrode material by using as stoppers the mask mat
    Type: Grant
    Filed: April 17, 2006
    Date of Patent: May 13, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Yagishita, Akio Kaneko, Kazunari Ishimaru
  • Publication number: 20080067673
    Abstract: A semiconductor device comprises: a semiconductor element; a mounting substrate with the semiconductor element mounted thereon; a first high thermal conductivity member formed on a surface of the mounting substrate; and a first cooling member thermally connected to at least a part of the first high thermal conductivity member. The first high thermal conductivity member is thermally connected to the semiconductor element, and the first high thermal conductivity member has an outer edge which is located outside an outer edge of the semiconductor element.
    Type: Application
    Filed: August 27, 2007
    Publication date: March 20, 2008
    Inventors: Tomonao Takamatsu, Hideo Aoki, Kazunari Ishimaru
  • Publication number: 20070147138
    Abstract: There is provided a semiconductor integrated circuit including a logic circuit and a writing circuit configured to receive a writing data outputted from the logic circuit, invert the writing data to generate an inverted data, compare the writing data with the inverted data and output the held writing data if the writing data is different from the inverted data.
    Type: Application
    Filed: December 20, 2006
    Publication date: June 28, 2007
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kazunari ISHIMARU
  • Patent number: 7235469
    Abstract: A semiconductor device suitable for the miniaturization and comprising properly controlled Si/SiGe gate electrode comprises an insulator formed on a semiconductor substrate, a first gate electrode formed on the insulator and including silicon-germanium, wherein a germanium concentration is higher near an interface to the insulator and lower in a surface side opposite to the insulator, and a second gate electrode formed on the insulator and including silicon-germanium, wherein a germanium concentration is substantially uniform and an n-type dopant of a concentration of above 6×1020 atoms/cm3 is contained.
    Type: Grant
    Filed: November 29, 2004
    Date of Patent: June 26, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasunori Okayama, Kiyotaka Miyano, Kazunari Ishimaru
  • Publication number: 20070090468
    Abstract: A semiconductor device includes a semiconductor substrate, an insulating film projected on a surface of the semiconductor substrate, a semiconductor film provided on a side surface of the insulating film, and MIS transistor formed in the semiconductor film, the MIS transistor having source, gate and drain region. The semiconductor device further includes a gate electrode provided on the gate region of the MIS transistor, the length of the gate electrode being larger than the thickness of the semiconductor film.
    Type: Application
    Filed: December 12, 2006
    Publication date: April 26, 2007
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hirohisa Kawasaki, Kazunari Ishimaru
  • Patent number: 7164175
    Abstract: A semiconductor device includes a semiconductor substrate, an insulating film projected on a surface of the semiconductor substrate, a semiconductor film provided on a side surface of the insulating film, and MIS transistor formed in the semiconductor film, the MIS transistor having source, gate and drain region. The semiconductor device further includes a gate electrode provided on the gate region of the MIS transistor, the length of the gate electrode being larger than the thickness of the semiconductor film.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: January 16, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirohisa Kawasaki, Kazunari Ishimaru
  • Publication number: 20070007566
    Abstract: A semiconductor device having a semiconductor substrate, a SRAM area formed in the semiconductor substrate, the SRAM area having first transistors, the first transistor having a metallic compound film formed on each of a source and a drain regions of the first transistor, and a logic circuit area formed in the semiconductor substrate, the logic circuit area having a second transistor, the second transistor having a metallic compound film on each of a source and a drain regions of the second transistor. The thickness of the metallic compound film of the second transistor is thicker than thickness of the metallic compound film of the first transistor.
    Type: Application
    Filed: July 6, 2006
    Publication date: January 11, 2007
    Inventor: Kazunari Ishimaru
  • Publication number: 20060278903
    Abstract: A semiconductor device includes a first semiconductor layer, and a first insulated-gate field-effect transistor of a first conductivity type that is provided in a major surface region of the first semiconductor layer. The semiconductor device further includes an electrostrictive layer that is provided on a back surface of the first semiconductor layer and applies a first stress along a channel length to a channel region of the first insulated-gate field-effect transistor when the first insulated-gate field-effect transistor is operated.
    Type: Application
    Filed: May 31, 2006
    Publication date: December 14, 2006
    Inventor: Kazunari Ishimaru
  • Publication number: 20060275988
    Abstract: According to the present invention, there is provided a semiconductor device fabrication method, comprising: depositing a mask material on a semiconductor substrate; patterning the mask material and forming a trench in a surface portion of the semiconductor substrate by etching, thereby forming a first projection in a first region, and a second projection wider than the first projection in a second region; burying a device isolation insulating film in the trench; etching away a predetermined amount of the device isolation insulating film formed in the first region; etching away the mask material formed in the second region; forming a first gate insulating film on a pair of opposing side surfaces of the first projection, and a second gate insulating film on an upper surface of the second projection; depositing a first gate electrode material on the device isolation insulating film, mask material, and second gate insulating film; planarizing the first gate electrode material by using as stoppers the mask materi
    Type: Application
    Filed: April 17, 2006
    Publication date: December 7, 2006
    Inventors: Atsushi Yagishita, Akio Kaneko, Kazunari Ishimaru
  • Patent number: 7129550
    Abstract: A semiconductor layer in which a primary part of a FinFET is formed, i.e., a fin has a shape which is long in a direction x and short in a direction y. A width of the fin in the direction y changes on three stages. First, in a channel area between gate electrodes each having a gate length Lg, the width of the fin in the direction y is Wch. Further, the width of the fin in the direction y in a source/drain extension area adjacent to the channel area in the direction x is Wext (>Wch). Furthermore, the width of the fin in the direction y in a source/drain area adjacent to the source/drain extension area in the direction x is Wsd (>Wext).
    Type: Grant
    Filed: February 9, 2004
    Date of Patent: October 31, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Fujiwara, Kazunari Ishimaru, Akira Hokazono