Patents by Inventor Kazunari Ishimaru

Kazunari Ishimaru has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060237788
    Abstract: A semiconductor device has a semiconductor substrate, a first MOSFET which has a first gate insulating film made of a high dielectric material formed above the semiconductor substrate and a first gate electrode formed above the first gate insulating film, an insulating film which is formed directly on sidewalls of the first gate electrode and made of a material having dielectric constant smaller than that of the first gate insulating film, and a second MOSFET which has a second gate insulating film made of a material having dielectric constant smaller than that of the first gate insulating film formed above the semiconductor substrate and a second gate electrode formed above the second gate insulating film, wherein the first gate electrode is formed of a first silicide or a first metal; and the second gate electrode is formed including a film made of at least one of polysilicon, amorphous silicon, polysilicon germanium and amorphous silicon germanium.
    Type: Application
    Filed: March 1, 2006
    Publication date: October 26, 2006
    Inventor: Kazunari Ishimaru
  • Publication number: 20060170047
    Abstract: A semiconductor device according to an embodiment of the present invention comprises a semiconductor substrate; and a plurality of MOSFETs which are formed on the semiconductor substrate, are the same conductivity type, and have gate insulating films of the same insulating material, with each gate insulating film having any one of a plurality of different thicknesses, and wherein a gate electrode of the MOSFET having a first gate insulating film of a small thickness, consisting substantially of silicide, and a gate electrode of a MOSFET having a second gate insulating film of a thickness larger than that of the first gate insulating film has a structure consisting of polycrystalline silicon, amorphous silicon or silicon-germanium and silicide formed on the polycrystalline silicon, amorphous silicon or germanium silicon.
    Type: Application
    Filed: December 9, 2005
    Publication date: August 3, 2006
    Inventor: Kazunari Ishimaru
  • Publication number: 20060166456
    Abstract: A semiconductor layer in which a primary part of a FinFET is formed, i.e., a fin has a shape which is long in a direction x and short in a direction y. A width of the fin in the direction y changes on three stages. First, in a channel area between gate electrodes each having a gate length Lg, the width of the fin in the direction y is Wch. Further, the width of the fin in the direction y in a source/drain extension area adjacent to the channel area in the direction x is Wext (>Wch). Furthermore, the width of the fin in the direction y in a source/drain area adjacent to the source/drain extension area in the direction x is Wsd (>Wext).
    Type: Application
    Filed: March 25, 2006
    Publication date: July 27, 2006
    Inventors: Makoto Fujiwara, Kazunari Ishimaru, Akira Hokazono
  • Patent number: 7061054
    Abstract: A semiconductor device has a first and a second semiconductor layer provided on an insulating film on a support substrate. A first memory cell transistor, which constitutes a part of a memory cell in an SRAM, has a first gate electrode of a first conductivity type and first source/drain diffusion layers of a second conductivity type opposite to the first conductivity type. The following expression is fulfilled the thickness of the first conductivity type?one-third of a length of the first gate electrode in its channel length. A first peripheral transistor, which constitutes a part of a peripheral circuit, has a third gate electrode and a third source/drain diffusion layers. The following expression is satisfied the thickness of the second semiconductor layer>one-third of a length of the third gate electrode in its channel length direction.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: June 13, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kanna Tomiye, Akira Hokazono, Kazunari Ishimaru
  • Publication number: 20060065934
    Abstract: A semiconductor device suitable for the miniaturization and comprising properly controlled Si/SiGe gate electrode comprises an insulator formed on a semiconductor substrate, a first gate electrode formed on the insulator and including silicon-germanium, wherein a germanium concentration is higher near an interface to the insulator and lower in a surface side opposite to the insulator, and a second gate electrode formed on the insulator and including silicon-germanium, wherein a germanium concentration is substantially uniform and an n-type dopant of a concentration of above 6×1020 atoms/cm3 is contained.
    Type: Application
    Filed: November 29, 2004
    Publication date: March 30, 2006
    Inventors: Yasunori Okayama, Kiyotaka Miyano, Kazunari Ishimaru
  • Publication number: 20050282354
    Abstract: A semiconductor device manufacturing method is disclosed. The method is to form a second semiconductor layer which has less susceptibility to adopting insulative characteristics than a first semiconductor layer on the first semiconductor layer. Then, grooves which expose portions of the second and first semiconductor layers are formed to extend from the upper surface of the second semiconductor layer into the first semiconductor layer. Next, portions of the first and second semiconductor layers which are exposed to the grooves are changed into an insulator form to fill the grooves with the insulator-form portions of the first semiconductor layer.
    Type: Application
    Filed: March 25, 2005
    Publication date: December 22, 2005
    Inventors: Hirohisa Kawasaki, Kazunari Ishimaru, Kunihiro Kasai, Yasunori Okayama
  • Patent number: 6977837
    Abstract: A semiconductor memory is formed of first, second, third, fourth, fifth and sixth field effect transistors. The first and second transistors have a first line as gates, one ends of current paths of the first and second transistors are connected to a reference potential electrode. The third and fourth transistors have a second line as gates, and one ends of current paths of the third and fourth transistors are connected to the reference electrode. The fifth transistor has a first word line as a gate, and one end of a current path of the fifth transistor is connected to the other ends of the current paths of the first and second transistors. The sixth transistor having a second word line as a gate, and one end of a current path of the sixth transistor is connected to the other ends of the current paths of the third and fourth transistors.
    Type: Grant
    Filed: March 18, 2004
    Date of Patent: December 20, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Watanabe, Kazunari Ishimaru
  • Publication number: 20050094434
    Abstract: A semiconductor memory is formed of first, second, third, fourth, fifth and sixth field effect transistors. The first and second transistors have a first line as gates, one ends of current paths of the first and second transistors are connected to a reference potential electrode. The third and fourth transistors have a second line as gates, and one ends of current paths of the third and fourth transistors are connected to the reference electrode. The fifth transistor has a first word line as a gate, and one end of a current path of the fifth transistor is connected to the other ends of the current paths of the first and second transistors. The sixth transistor having a second word line as a gate, and one end of a current path of the sixth transistor is connected to the other ends of the current paths of the third and fourth transistors.
    Type: Application
    Filed: March 18, 2004
    Publication date: May 5, 2005
    Inventors: Takeshi Watanabe, Kazunari Ishimaru
  • Publication number: 20050051825
    Abstract: A semiconductor layer in which a primary part of a FinFET is formed, i.e., a fin has a shape which is long in a direction x and short in a direction y. A width of the fin in the direction y changes on three stages. First, in a channel area between gate electrodes each having a gate length Lg, the width of the fin in the direction y is Wch. Further, the width of the fin in the direction y in a source/drain extension area adjacent to the channel area in the direction x is Wext (>Wch). Furthermore, the width of the fin in the direction y in a source/drain area adjacent to the source/drain extension area in the direction x is Wsd (>Wext).
    Type: Application
    Filed: February 9, 2004
    Publication date: March 10, 2005
    Inventors: Makoto Fujiwara, Kazunari Ishimaru, Akira Hokazono
  • Publication number: 20050026377
    Abstract: A semiconductor device includes a semiconductor substrate, an insulating film projected on a surface of the semiconductor substrate, a semiconductor film provided on a side surface of the insulating film, and MIS transistor formed in the semiconductor film, the MIS transistor having source, gate and drain region. The semiconductor device further includes a gate electrode provided on the gate region of the MIS transistor, the length of the gate electrode being larger than the thickness of the semiconductor film.
    Type: Application
    Filed: April 28, 2004
    Publication date: February 3, 2005
    Inventors: Hirohisa Kawasaki, Kazunari Ishimaru
  • Publication number: 20040259295
    Abstract: A semiconductor device has a first and a second semiconductor layer provided on an insulating film on a support substrate. A first memory cell transistor, which constitutes a part of a memory cell in an SRAM, has a first gate electrode of a first conductivity type and first source/drain diffusion layers of a second conductivity type opposite to the first conductivity type. The following expression is fulfilled the thickness of the first conductivity type≦one-third of a length of the first gate electrode in its channel length. A first peripheral transistor, which constitutes a part of a peripheral circuit, has a third gate electrode and a third source/drain diffusion layers. The following expression is satisfied the thickness of the second semiconductor layer>one-third of a length of the third gate electrode in its channel length direction.
    Type: Application
    Filed: October 8, 2003
    Publication date: December 23, 2004
    Inventors: Kanna Tomiye, Akira Hokazono, Kazunari Ishimaru
  • Patent number: 6656826
    Abstract: A semiconductor device has a fuse to be blown with an energy beam. The semiconductor device has copper wiring levels formed on a semiconductor substrate on which semiconductor elements are formed, an uppermost wiring level formed on said copper wiring levels and including a refractory metal film connected to a top one of the copper wiring levels, the fuse formed from a part of the uppermost wiring level, and a surface protective film formed on the uppermost wiring level.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: December 2, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazunari Ishimaru
  • Patent number: 6627528
    Abstract: Gate electrodes in an inverter section and a transfer section are formed only on element areas, and connected to each other by means of local interconnection layers. As a result, a memory cell of a very small size but a large capacity can be formed without considering a gate fringe or shortening phenomenon problem.
    Type: Grant
    Filed: August 30, 2000
    Date of Patent: September 30, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazunari Ishimaru
  • Patent number: 6365472
    Abstract: A semiconductor device comprises an LDD structure MOS transistor wherein the formation of defects due to ion implantation at the edge of the side wall of the gate electrode is suppressed. In order to perform the ion implantation for forming the source and drain regions of the MOS transistor, impurity ions are implanted using the first and second side walls provided to the gate electrode as a mask, and then the heat treatment for impurity activation is performed after removing the second side wall near the source and drain regions doped with high-concentration impurity ions. By removing the second side wall prior to the heat treatment, the stress applied to the edges of the high-concentration impurity doped regions in an amorphous state is decreased. The defects therefore can be suppressed from being formed at the edges of the source and drain regions near the gate electrode in the recrystallization of the amorphous layer by the heat treatment.
    Type: Grant
    Filed: September 2, 1999
    Date of Patent: April 2, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazunari Ishimaru, Fumitomo Matsuoka, Kaori Umezawa
  • Publication number: 20020037643
    Abstract: A semiconductor device has a fuse to be blown with an energy beam. The semiconductor device has copper wiring levels formed on a semiconductor substrate on which semiconductor elements are formed, an uppermost wiring level formed on said copper wiring levels and including a refractory metal film connected to a top one of the copper wiring levels, the fuse formed from a part of the uppermost wiring level, and a surface protective film formed on the uppermost wiring level.
    Type: Application
    Filed: September 27, 2001
    Publication date: March 28, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kazunari Ishimaru
  • Patent number: 6355982
    Abstract: In a SRAM, coupling between the adjacent bit lines is reduced and the limitation in reduction of the pattern area per memory cell is relaxed. The SRAM comprises SRAM memory cells arranged in a matrix and forming a cell array, pairs of bit lines BL and /BL extending in a column direction of the memory cell array, each of the pairs of bit lines being connected in common to the memory cells on the same column of the cell array, and the bit lines of each pair being arranged on both sides of the memory cells on the same column, a grounded line Vss, for supplying a ground potential to the memory cells, formed of the same layer as that of the pairs of bit lines and extending in the column direction, and a power supplying line Vdd, for supplying a power potential to the memory cells, formed of a layer different from that of the pairs of bit lines.
    Type: Grant
    Filed: December 15, 1998
    Date of Patent: March 12, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazunari Ishimaru, Fumitomo Matsuoka
  • Publication number: 20020011610
    Abstract: In a SRAM, coupling between the adjacent bit lines is reduced and the limitation in reduction of the pattern area per memory cell is relaxed. The SRAM comprises SRAM memory cells arranged in a matrix and forming a cell array, pairs of bit lines BL and /BL extending in a column direction of the memory cell array, each of the pairs of bit lines being connected in common to the memory cells on the same column of the cell array, and the bit lines of each pair being arranged on both sides of the memory cells on the same column, a grounded line Vss, for supplying a ground potential to the memory cells, formed of the same layer as that of the pairs of bit lines and extending in the column direction, and a power supplying line Vdd, for supplying a power potential to the memory cells, formed of a layer different from that of the pairs of bit lines.
    Type: Application
    Filed: December 15, 1998
    Publication date: January 31, 2002
    Inventors: KAZUNARI ISHIMARU, FUMITOMO MATSUOKA
  • Publication number: 20010038552
    Abstract: A semiconductor memory with static memory cells has an n-well in which pMOS transistors are formed and a p-well in which nMOS transistors are formed. The n- and p-wells are divided into blocks each containing a given number of memory cells. The n- and p-wells in each block receive voltages that vary depending on whether or not the memory cells are selected. If the memory cells are selected to operate, the threshold voltage of each transistor in the memory cells is decreased to increase current to be taken out of the memory cells. If the memory cells are not selected, the threshold voltage is increased to reduce leakage current of the memory cells. This arrangement suppresses standby current and improves the operation speed of the memory cells.
    Type: Application
    Filed: March 23, 2001
    Publication date: November 8, 2001
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kazunari Ishimaru
  • Patent number: 6066543
    Abstract: A method of manufacturing a semiconductor device includes the steps of forming a trench for isolating an element region on a semiconductor substrate, burying a first oxide film in the trench so as to contact a surface of the trench, flattening a surface of the first oxide film, heating the semiconductor substrate to form a second oxide film at an interface between the surface of the trench and the first oxide film, and annealing the semiconductor substrate.
    Type: Grant
    Filed: April 10, 1998
    Date of Patent: May 23, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Minoru Takahashi, Fumitomo Matsuoka, Kazunari Ishimaru
  • Patent number: 5998849
    Abstract: A semiconductor device comprises an LDD structure MOS transistor wherein the formation of defects due to ion implantation at the edge of the side wall of the gate electrode is suppressed. In order to perform the ion implantation for forming the source and drain regions of the MOS transistor, impurity ions are implanted using the first and second side walls provided to the gate electrode as a mask, and then the heat treatment for impurity activation is performed after removing the second side wall near the source and drain regions doped with high-concentration impurity ions. By removing the second side wall prior to the heat treatment, the stress applied to the edges of the high-concentration impurity doped regions in an amorphous state is decreased. The defects therefore can be suppressed from being formed at the edges of the source and drain regions near the gate electrode in the recrystallization of the amorphous layer by the heat treatment.
    Type: Grant
    Filed: December 15, 1997
    Date of Patent: December 7, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazunari Ishimaru, Fumitomo Matsuoka, Kaori Umezawa