Patents by Inventor Kazunori Hagimoto

Kazunori Hagimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240079412
    Abstract: A nitride semiconductor substrate, including a Ga-containing nitride semiconductor thin film formed on a substrate for film-forming in which a single crystal silicon layer is formed above a supporting substrate via an insulative layer, wherein the nitride semiconductor substrate has a region where the Ga-containing nitride semiconductor thin film is not formed inward from an edge of the single crystal silicon layer being a growth surface of the nitride semiconductor thin film. This provides: a nitride semiconductor substrate with inhibited generation of a reaction mark; and a manufacturing method therefor.
    Type: Application
    Filed: January 17, 2022
    Publication date: March 7, 2024
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Ippei KUBONO, Keitaro TSUCHIYA, Kazunori HAGIMOTO, Masaru SHINOMIYA
  • Publication number: 20230279581
    Abstract: A method for producing a nitride semiconductor wafer, in which a nitride semiconductor thin film is grown on a silicon single crystal substrate by vapor phase growth, includes, by using a silicon single crystal substrate having a resistivity of 1000 ?·cm or more, an oxygen concentration of less than 1×1017 atoms/cm3 and a thickness of 1000 ?m or more, growing the nitride semiconductor thin film on the silicon single crystal substrate by vapor phase growth. As a result, a method produces a nitride semiconductor wafer in which plastic deformation and warpage are suppressed even in the case of a high-resistivity, ultra-low oxygen concentration silicon single crystal substrate, which is promising as a support substrate for high frequency devices.
    Type: Application
    Filed: April 8, 2021
    Publication date: September 7, 2023
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Keitaro TSUCHIYA, Masaru SHINOMIYA, Kazunori HAGIMOTO, Ippei KUBONO
  • Patent number: 11705330
    Abstract: A substrate for an electronic device, including a nitride semiconductor film formed on a joined substrate including a silicon single crystal, where the joined substrate has a plurality of silicon single crystal substrates that are joined and has a thickness of more than 2000 ?m, and the plurality of silicon single crystal substrates are produced by a CZ method and have a resistivity of 0.1 ?cm or lower. This provides: a substrate for an electronic device having a nitride semiconductor film formed on a silicon substrate, where the substrate for an electronic device can suppress a warp and can also be used for a product with a high breakdown voltage; and a method for producing the same.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: July 18, 2023
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Kazunori Hagimoto, Shouzaburo Goto
  • Publication number: 20220367188
    Abstract: The present invention is a substrate for an electronic device, including a nitride semiconductor film formed on a joined substrate including a silicon single crystal, where the joined substrate has at least a bond wafer including a silicon single crystal joined on a base wafer including a silicon single crystal, the base wafer includes CZ silicon having a resistivity of 0.1 ?cm or lower and a crystal orientation of <100>, and the bond wafer has a crystal orientation of <111>. This provides a substrate for an electronic device, having a suppressed warp.
    Type: Application
    Filed: July 2, 2020
    Publication date: November 17, 2022
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Kazunori HAGIMOTO, Shouzaburo GOTO
  • Publication number: 20220238326
    Abstract: A substrate for an electronic device, including a nitride semiconductor film formed on a joined substrate including a silicon single crystal, where the joined substrate has a plurality of silicon single crystal substrates that are joined and has a thickness of more than 2000 ?m, and the plurality of silicon single crystal substrates are produced by a CZ method and have a resistivity of 0.1 ?cm or lower. This provides: a substrate for an electronic device having a nitride semiconductor film formed on a silicon substrate, where the substrate for an electronic device can suppress a warp and can also be used for a product with a high breakdown voltage; and a method for producing the same.
    Type: Application
    Filed: April 30, 2020
    Publication date: July 28, 2022
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Kazunori HAGIMOTO, Shouzaburo GOTO
  • Publication number: 20210358738
    Abstract: A method for manufacturing an epitaxial wafer including the steps of: preparing a silicon-based substrate having a chamfered portion in a peripheral portion; forming an annular trench in the chamfered portion of the silicon-based substrate along an internal periphery of the chamfered portion; and performing an epitaxial growth on the silicon-based substrate having the trench formed. This provides a method for manufacturing an epitaxial wafer by which a crack generated in a peripheral chamfered portion can be suppressed from extending towards the center.
    Type: Application
    Filed: September 6, 2019
    Publication date: November 18, 2021
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Keitarou TSUCHIYA, Kazunori HAGIMOTO, Masaru SHINOMIYA
  • Patent number: 10833184
    Abstract: A semiconductor device substrate including: a substrate; a buffer layer which is provided on the substrate and made of a nitride semiconductor; and a device active layer which is formed of a nitride semiconductor layer provided on the buffer layer, the semiconductor device substrate in that the buffer layer includes: a first region which contains carbon and iron; a second region which is provided on the first region and has average concentration of iron lower than that in the first region and average concentration of carbon higher than that in the first region, and the average concentration of the carbon in the second region is lower than the average concentration of the iron in the first region. The semiconductor device substrate which can suppress a transverse leak current in a high-temperature operation of a device while suppressing a longitudinal leak current and can inhibit a current collapse phenomenon is provided.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: November 10, 2020
    Assignees: SANKEN ELECTRIC CO., LTD., SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Ken Sato, Hiroshi Shikauchi, Masaru Shinomiya, Keitaro Tsuchiya, Kazunori Hagimoto
  • Patent number: 10586701
    Abstract: Semiconductor base including: silicon-based substrate; buffer layer including first and second layers alternately on silicon-based substrate, first layer made of nitride-based compound semiconductor containing first material, second layer made of nitride-based compound semiconductor containing second material having larger lattice constant than first material; channel layer on buffer layer and made of nitride-based compound semiconductor containing second material, buffer layer has: first composition graded layer between at least one of first layers and second layer immediately thereabove, made of nitride-based compound semiconductor whose composition ratio of second material is increased gradually upward, whose composition ratio of first material is decreased gradually upward; second composition graded layer between at least one of second layers and first layer immediately thereabove, made of nitride-based compound semiconductor whose first material is increased gradually upward, whose composition ratio of s
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: March 10, 2020
    Assignees: SANKEN ELECTRIC CO., LTD., SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Hiroshi Shikauchi, Ken Sato, Masaru Shinomiya, Keitaro Tsuchiya, Kazunori Hagimoto
  • Patent number: 10553674
    Abstract: A substrate for semiconductor device includes a substrate, a buffer layer which is provided on the substrate and made of a nitride semiconductor, and a device active layer which is provided on the buffer layer and composed of a nitride semiconductor layer, wherein the buffer layer contains carbon and iron, a carbon concentration of an upper surface of the buffer layer is higher than a carbon concentration of a lower surface of the buffer layer, and an iron concentration of the upper surface of the buffer layer is lower than an iron concentration of the lower surface of the buffer layer. As a result, the substrate for semiconductor device can reduce a leak current in a lateral direction at the time of a high-temperature operation while suppressing a leak current in a longitudinal direction.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: February 4, 2020
    Assignees: SANKEN ELECTRIC CO., LTD., SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Ken Sato, Hiroshi Shikauchi, Hirokazu Goto, Masaru Shinomiya, Keitaro Tsuchiya, Kazunori Hagimoto
  • Patent number: 10529842
    Abstract: A semiconductor base substance includes: a substrate; a buffer layer which is made of a nitride semiconductor and provided on the substrate; and a channel layer which is made of a nitride semiconductor and provided on the buffer layer, wherein the buffer layer includes: a first region which is provided on the substrate side and has boron concentration higher than acceptor element concentration; and a second region which is provided on the first region, and has boron concentration lower than that in the first region and acceptor element concentration higher than that in the first region. As a result, the semiconductor base substance which can obtain a high pit suppression effect while maintaining a high longitudinal breakdown voltage is provided.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: January 7, 2020
    Assignees: SANKEN ELECTRIC CO., LTD., SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Hiroshi Shikauchi, Ken Sato, Masaru Shinomiya, Keitaro Tsuchiya, Kazunori Hagimoto
  • Publication number: 20190214492
    Abstract: A semiconductor device substrate including: a substrate; a buffer layer which is provided on the substrate and made of a nitride semiconductor; and a device active layer which is formed of a nitride semiconductor layer provided on the buffer layer, the semiconductor device substrate in that the buffer layer includes: a first region which contains carbon and iron; a second region which is provided on the first region and has average concentration of iron lower than that in the first region and average concentration of carbon higher than that in the first region, and the average concentration of the carbon in the second region is lower than the average concentration of the iron in the first region. The semiconductor device substrate which can suppress a transverse leak current in a high-temperature operation of a device while suppressing a longitudinal leak current and can inhibit a current collapse phenomenon is provided.
    Type: Application
    Filed: February 24, 2017
    Publication date: July 11, 2019
    Applicants: SANKEN ELECTRIC CO., LTD., SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Ken SATO, Hiroshi SHIKAUCHI, Masaru SHINOMIYA, Keitaro TSUCHIYA, Kazunori HAGIMOTO
  • Patent number: 10319587
    Abstract: A method of manufacturing an epitaxial wafer having an epitaxial layer on a silicon-based substrate, the method of manufacturing the epitaxial wafer including epitaxially growing a semiconductor layer on the silicon-based substrate after applying terrace processing to an outer peripheral portion of the silicon-based substrate. As a result, the method of manufacturing the epitaxial wafer having the epitaxial layer on the silicon-based substrate in which an epitaxial wafer which is completely free from cracks can be obtained, is provided.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: June 11, 2019
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Kazunori Hagimoto, Masaru Shinomiya, Keitaro Tsuchiya, Hirokazu Goto, Ken Sato, Hiroshi Shikauchi, Shoichi Kobayashi, Hirotaka Kurimoto
  • Publication number: 20190051515
    Abstract: Semiconductor base including: silicon-based substrate; buffer layer including first and second layers alternately on silicon-based substrate, first layer made of nitride-based compound semiconductor containing first material, second layer made of nitride-based compound semiconductor containing second material having larger lattice constant than first material; channel layer on buffer layer and made of nitride-based compound semiconductor containing second material, buffer layer has: first composition graded layer between at least one of first layers and second layer immediately thereabove, made of nitride-based compound semiconductor whose composition ratio of second material is increased gradually upward, whose composition ratio of first material is decreased gradually upward; second composition graded layer between at least one of second layers and first layer immediately thereabove, made of nitride-based compound semiconductor whose first material is increased gradually upward, whose composition ratio of s
    Type: Application
    Filed: February 26, 2016
    Publication date: February 14, 2019
    Applicants: SANKEN ELECTRIC CO., LTD., SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Hiroshi SHIKAUCHI, Ken SATO, Masaru SHINOMIYA, Keitaro TSUCHIYA, Kazunori HAGIMOTO
  • Patent number: 10115589
    Abstract: An epitaxial substrate for electronic devices, including: a Si-based substrate; an AlN initial layer provided on the Si-based substrate; and a buffer layer provided on the AlN initial layer, wherein the roughness Sa of the surface of the AlN initial layer on the side where the buffer layer is located is 4 nm or more. As a result, an epitaxial substrate for electronic devices, in which V pits in a buffer layer structure can be suppressed and longitudinal leakage current characteristics can be improved when an electronic device is fabricated therewith, is provided.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: October 30, 2018
    Assignees: SHIN-ETSU HANDOTAI CO., LTD., SANKEN ELECTRIC CO., LTD.
    Inventors: Kazunori Hagimoto, Masaru Shinomiya, Keitaro Tsuchiya, Hirokazu Goto, Ken Sato, Hiroshi Shikauchi
  • Publication number: 20180269316
    Abstract: A semiconductor base substance includes: a substrate; a buffer layer which is made of a nitride semiconductor and provided on the substrate; and a channel layer which is made of a nitride semiconductor and provided on the buffer layer, wherein the buffer layer includes: a first region which is provided on the substrate side and has boron concentration higher than acceptor element concentration; and a second region which is provided on the first region, and has boron concentration lower than that in the first region and acceptor element concentration higher than that in the first region. As a result, the semiconductor base substance which can obtain a high pit suppression effect while maintaining a high longitudinal breakdown voltage is provided.
    Type: Application
    Filed: August 29, 2016
    Publication date: September 20, 2018
    Applicants: SANKEN ELECTRIC CO., LTD., SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Hiroshi SHIKAUCHI, Ken SATO, Masaru SHINOMIYA, Keitaro TSUCHIYA, Kazunori HAGIMOTO
  • Patent number: 10068985
    Abstract: A method for manufacturing a semiconductor substrate, the semiconductor substrate including: a substrate; an initial layer provided on the substrate; a high-resistance layer provided on the initial layer which is composed of a nitride-based semiconductor and contains carbon; and a channel layer provided on the high-resistance layer which is composed of a nitride-based semiconductor, and at a step of forming the high-resistance layer, a gradient is given to a preset temperature at which the semiconductor substrate is heated, and the high-resistance layer is formed such that the preset temperature at the start of formation of the high-resistance layer is different from the preset temperature at the end of formation of the high-resistance layer. It is possible to provide the method for manufacturing a semiconductor substrate, which can reduce a concentration gradient of carbon concentration in the high-resistance layer and also provide a desired value for the carbon concentration.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: September 4, 2018
    Assignees: SANKEN ELECTRIC CO., LTD., SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Ken Sato, Hiroshi Shikauchi, Hirokazu Goto, Masaru Shinomiya, Keitaro Tsuchiya, Kazunori Hagimoto
  • Publication number: 20180245240
    Abstract: A method for producing a semiconductor epitaxial wafer, including steps of: fabricating an epitaxial wafer by epitaxially growing a semiconductor layer on a silicon-based substrate; observing the outer edge portion of the fabricated epitaxial wafer; and removing portions in which a crack, epitaxial layer peeling, and a reaction mark observed in the step of observing are present. As a result, a method for producing a semiconductor epitaxial wafer in which a completely crack-free semiconductor epitaxial wafer can be obtained, is provided.
    Type: Application
    Filed: February 22, 2018
    Publication date: August 30, 2018
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Kazunori HAGIMOTO, Masaru SHINOMIYA, Keitaro TSUCHIYA, Hirokazu GOTO, Ken SATO, Hiroshi SHIKAUCHI, Shoichi KOBAYASHI, Hirotaka KURIMOTO
  • Publication number: 20180204908
    Abstract: A substrate for semiconductor device includes a substrate, a buffer layer which is provided on the substrate and made of a nitride semiconductor, and a device active layer which is provided on the buffer layer and composed of a nitride semiconductor layer, wherein the buffer layer contains carbon and iron, a carbon concentration of an upper surface of the buffer layer is higher than a carbon concentration of a lower surface of the buffer layer, and an iron concentration of the upper surface of the buffer layer is lower than an iron concentration of the lower surface of the buffer layer. As a result, the substrate for semiconductor device can reduce a leak current in a lateral direction at the time of a high-temperature operation while suppressing a leak current in a longitudinal direction.
    Type: Application
    Filed: June 17, 2016
    Publication date: July 19, 2018
    Applicants: SANKEN ELECTRIC CO., LTD., SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Ken SATO, Hiroshi SHIKAUCHI, Hirokazu GOTO, Masaru SHINOMIYA, Keitaro TSUCHIYA, Kazunori HAGIMOTO
  • Patent number: 9966259
    Abstract: A silicon-based substrate on which a nitride compound semiconductor layer is formed on a front surface thereof, including a first portion provided on the front surface side which has a first impurity concentration and a second portion provided on an inner side of the first portion which has a second impurity concentration higher than the first impurity concentration, wherein the first impurity concentration being 1×1014 atoms/cm3 or more and less than 1×1019 atoms/cm3. Consequently, there is provided the silicon-based substrate in which the crystallinity of the nitride compound semiconductor layer formed on an upper side thereof can be maintained excellently while improving a warpage of the substrate.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: May 8, 2018
    Assignees: SHANKEN ELECTRIC CO., LTD., SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Hiroshi Shikauchi, Ken Sato, Hirokazu Goto, Masaru Shinomiya, Keitaro Tsuchiya, Kazunori Hagimoto
  • Patent number: 9938638
    Abstract: A method for producing a semiconductor epitaxial wafer, including steps of: fabricating an epitaxial wafer by epitaxially growing a semiconductor layer on a silicon-based substrate; observing the outer edge portion of the fabricated epitaxial wafer; and removing portions in which a crack, epitaxial layer peeling, and a reaction mark observed in the step of observing are present. As a result, a method for producing a semiconductor epitaxial wafer in which a completely crack-free semiconductor epitaxial wafer can be obtained, is provided.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: April 10, 2018
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Kazunori Hagimoto, Masaru Shinomiya, Keitaro Tsuchiya, Hirokazu Goto, Ken Sato, Hiroshi Shikauchi, Shoichi Kobayashi, Hirotaka Kurimoto