Patents by Inventor Kazunori Hagimoto

Kazunori Hagimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9876101
    Abstract: A semiconductor substrate including a substrate, a buffer layer having a nitride-based semiconductor containing carbon provided on the substrate, a high-resistance layer having a nitride-based semiconductor containing carbon provided on the buffer layer, and a channel layer having a nitride-based semiconductor provided on the high-resistance layer, the high-resistance layer including a first region having carbon concentration lower than that of the buffer layer, and a second region which is provided between the first region and the channel layer, and has the carbon concentration higher than the first region.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: January 23, 2018
    Assignees: SANKEN ELECTRIC CO., LTD., SHIN-ETSU HANDOTAI CO., LTD
    Inventors: Ken Sato, Hiroshi Shikauchi, Hirokazu Goto, Masaru Shinomiya, Kazunori Hagimoto, Keitaro Tsuchiya
  • Publication number: 20170352537
    Abstract: An epitaxial substrate for electronic devices, including: a Si-based substrate; an AlN initial layer provided on the Si-based substrate; and a buffer layer provided on the AlN initial layer, wherein the roughness Sa of the surface of the AlN initial layer on the side where the buffer layer is located is 4 nm or more. As a result, an epitaxial substrate for electronic devices, in which V pits in a buffer layer structure can be suppressed and longitudinal leakage current characteristics can be improved when an electronic device is fabricated therewith, is provided.
    Type: Application
    Filed: December 18, 2015
    Publication date: December 7, 2017
    Applicants: SHIN-ETSU HANDOTAI CO., LTD., SANKEN ELECTRIC CO., LTD.
    Inventors: Kazunori HAGIMOTO, Masaru SHINOMIYA, Keitaro TSUCHIYA, Hirokazu GOTO, Ken SATO, Hiroshi SHIKAUCHI
  • Publication number: 20170323960
    Abstract: An epitaxial wafer including: a silicon-based substrate; a first buffer layer on the substrate and including a first multilayer structure buffer region composed of AlxGa1-xN layers and AlyGa1-yN layers (x>y) alternately disposed and a first insertion layer composed of an AlzGa1-zN layer (x>z) and is thicker than the AlyGa1-yN layer, the first regions and insertion layers alternately disposed; a second buffer layer on the first and including a second multilayer structure buffer region composed of Al?Ga1-?N layers and Al?Ga1-?N layers (?>?) alternately disposed and a second insertion layer composed of an Al?Ga1-?N layer (?>?) and is thicker than the Al?Ga1-?N layer, the second regions and insertion layers alternately disposed; and a channel layer on the second buffer layer and thicker than the second insertion layer. The average Al composition in the second buffer layer is higher than that in the first.
    Type: Application
    Filed: November 6, 2015
    Publication date: November 9, 2017
    Applicants: SANKEN ELECTRIC CO., LTD., SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Ken SATO, Hiroshi SHIKAUCHI, Hirokazu GOTO, Masaru SHINOMIYA, Keitaro TSUCHIYA, Kazunori HAGIMOTO
  • Publication number: 20170236711
    Abstract: A silicon-based substrate on which a nitride compound semiconductor layer is formed on a front surface thereof, including a first portion provided on the front surface side which has a first impurity concentration and a second portion provided on an inner side of the first portion which has a second impurity concentration higher than the first impurity concentration, wherein the first impurity concentration being 1×1014 atoms/cm3 or more and less than 1×1019 atoms/cm3. Consequently, there is provided the silicon-based substrate in which the crystallinity of the nitride compound semiconductor layer formed on an upper side thereof can be maintained excellently while improving a warpage of the substrate.
    Type: Application
    Filed: May 3, 2017
    Publication date: August 17, 2017
    Applicants: SANKEN ELECTRIC CO., LTD., SHIN-ETSU HANDOTAI CO. LTD.
    Inventors: Hiroshi SHIKAUCHI, Ken SATO, Hirokazu GOTO, Masaru SHINOMIYA, Keitaro TSUCHIYA, Kazunori HAGIMOTO
  • Patent number: 9673052
    Abstract: A silicon-based substrate on which a nitride compound semiconductor layer is formed on a front surface thereof, including a first portion provided on the front surface side which has a first impurity concentration and a second portion provided on an inner side of the first portion which has a second impurity concentration higher than the first impurity concentration, wherein the first impurity concentration being 1×1014 atoms/atomscm3 or more and less than 1×1019 atoms/cm3. Consequently, there is provided the silicon-based substrate in which the crystallinity of the nitride compound semiconductor layer formed on an upper side thereof can be maintained excellently while improving a warpage of the substrate.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: June 6, 2017
    Assignees: SANKEN ELECTRIC CO., LTD., SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Hiroshi Shikauchi, Ken Sato, Hirokazu Goto, Masaru Shinomiya, Keitaro Tsuchiya, Kazunori Hagimoto
  • Publication number: 20170133217
    Abstract: A semiconductor substrate including: substrate; buffer layer provided on substrate; high-resistance layer provided on buffer layer, high-resistance layer being composed of nitride-based semiconductor and containing transition metal and carbon; and channel layer provided on high-resistance layer, channel layer being composed of nitride-based semiconductor, wherein high-resistance layer includes reduction layer in contact with channel layer, reduction layer being layer in which concentration of transition metal is reduced from side where buffer layer is located toward side where channel layer is located, and reduction rate at which carbon concentration is reduced toward channel layer is higher than reduction rate at which concentration of transition metal is reduced toward channel layer.
    Type: Application
    Filed: March 5, 2015
    Publication date: May 11, 2017
    Applicants: SANKEN ELECTRIC CO., LTD., SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Ken SATO, Hiroshi SHIKAUCHI, Hirokazu GOTO, Masaru SHINOMIYA, Keitaro TSUCHIYA, Kazunori HAGIMOTO
  • Publication number: 20170117385
    Abstract: A method for manufacturing a semiconductor substrate, the semiconductor substrate including: a substrate; an initial layer provided on the substrate; a high-resistance layer provided on the initial layer which is composed of a nitride-based semiconductor and contains carbon; and a channel layer provided on the high-resistance layer which is composed of a nitride-based semiconductor, and at a step of forming the high-resistance layer, a gradient is given to a preset temperature at which the semiconductor substrate is heated, and the high-resistance layer is formed such that the preset temperature at the start of formation of the high-resistance layer is different from the preset temperature at the end of formation of the high-resistance layer. It is possible to provide the method for manufacturing a semiconductor substrate, which can reduce a concentration gradient of carbon concentration in the high-resistance layer and also provide a desired value for the carbon concentration.
    Type: Application
    Filed: March 5, 2015
    Publication date: April 27, 2017
    Applicants: SANKEN ELECTRIC CO., LTD., SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Ken SATO, Hiroshi SHIKAUCHI, Hirokazu GOTO, Masaru SHINOMIYA, Keitaro TSUCHIYA, Kazunori HAGIMOTO
  • Publication number: 20170029977
    Abstract: A method for producing a semiconductor epitaxial wafer, including steps of: fabricating an epitaxial wafer by epitaxially growing a semiconductor layer on a silicon-based substrate; observing the outer edge portion of the fabricated epitaxial wafer; and removing portions in which a crack, epitaxial layer peeling, and a reaction mark observed in the step of observing are present. As a result, a method for producing a semiconductor epitaxial wafer in which a completely crack-free semiconductor epitaxial wafer can be obtained, is provided.
    Type: Application
    Filed: February 10, 2015
    Publication date: February 2, 2017
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Kazunori HAGIMOTO, Masaru SHINOMIYA, Keitaro TSUCHIYA, Hirokazu GOTO, Ken SATO, Hiroshi SHIKAUCHI, Shoichi KOBAYASHI, Hirotaka KURIMOTO
  • Publication number: 20170033209
    Abstract: A semiconductor substrate including a substrate, a buffer layer having a nitride-based semiconductor containing carbon provided on the substrate, a high-resistance layer having a nitride-based semiconductor containing carbon provided on the buffer layer, and a channel layer having a nitride-based semiconductor provided on the high-resistance layer, the high-resistance layer including a first region having carbon concentration lower than that of the buffer layer, and a second region which is provided between the first region and the channel layer, and has the carbon concentration higher than the first region.
    Type: Application
    Filed: March 12, 2015
    Publication date: February 2, 2017
    Applicants: SANKEN ELECTRIC CO., LTD., SHIN-ETSU HANDOTAI CO. LTD.
    Inventors: Ken SATO, Hiroshi SHIKAUCHI, Hirokazu GOTO, Masaru SHINOMIYA, Kazunori HAGIMOTO, Keitaro TSUCHIYA
  • Publication number: 20160365239
    Abstract: A method of manufacturing an epitaxial wafer having an epitaxial layer on a silicon-based substrate, the method of manufacturing the epitaxial wafer including epitaxially growing a semiconductor layer on the silicon-based substrate after applying terrace processing to an outer peripheral portion of the silicon-based substrate. As a result, the method of manufacturing the epitaxial wafer having the epitaxial layer on the silicon-based substrate in which an epitaxial wafer which is completely free from cracks can be obtained, is provided.
    Type: Application
    Filed: February 10, 2015
    Publication date: December 15, 2016
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Kazunori HAGIMOTO, Masaru SHINOMIYA, Keitaro TSUCHIYA, Hirokazu GOTO, Ken SATO, Hiroshi SHIKAUCHI, Shoichi KOBAYASHI, Hirotaka KURIMOTO
  • Patent number: 9520286
    Abstract: A semiconductor substrate having a silicon-based substrate, a buffer layer provided on the silicon-based substrate and made of a nitride semiconductor containing boron, and an operation layer formed on the buffer layer, wherein a concentration of boron in the buffer layer gradually decreasing toward a side of the operation layer from a side of the silicon-based substrate. Thereby, the semiconductor substrate in which the buffer layer contains boron sufficient to obtain a dislocation suppression effect and boron is not diffused to the operation layer is provided.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: December 13, 2016
    Assignees: SHANKEN ELECTRIC CO., LTD., SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Hiroshi Shikauchi, Ken Sato, Hirokazu Goto, Masaru Shinomiya, Keitaro Tsuchiya, Kazunori Hagimoto
  • Patent number: 9401420
    Abstract: Semiconductor device including: silicon-based substrate; first buffer layer on silicon-based substrate and is formed of first layer containing Al composition and second layer containing less Al than the first layer, the first and second layers being alternately stacked; second buffer layer on the first buffer layer and is formed of third layer containing Al composition and fourth layer containing less Al than the third layer, the third and fourth layers being alternately stacked; and third buffer layer on the second buffer layer and is formed of fifth layer containing Al composition and sixth layer containing less Al than the fifth layer, the fifth and sixth layers being alternately stacked, wherein the second buffer layer contains more Al than the first and third buffer layers. Thus, the semiconductor device leakage can be suppressed while reducing stress which is applied to buffer layer and can improve flatness of active layer upper face.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: July 26, 2016
    Assignees: SHANKEN ELECTRIC CO., LTD., SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Hiroshi Shikauchi, Ken Sato, Hirokazu Goto, Masaru Shinomiya, Keitaro Tsuchiya, Kazunori Hagimoto
  • Publication number: 20160126099
    Abstract: A silicon-based substrate on which a nitride compound semiconductor layer is formed on a front surface thereof, including a first portion provided on the front surface side which has a first impurity concentration and a second portion provided on an inner side of the first portion which has a second impurity concentration higher than the first impurity concentration, wherein the first impurity concentration being 1×1014 atoms/atomscm3 or more and less than 1×1019 atoms/cm3. Consequently, there is provided the silicon-based substrate in which the crystallinity of the nitride compound semiconductor layer formed on an upper side thereof can be maintained excellently while improving a warpage of the substrate.
    Type: Application
    Filed: May 2, 2014
    Publication date: May 5, 2016
    Inventors: Hiroshi SHIKAUCHI, Ken SATO, Hirokazu GOTO, Masaru SHINOMIYA, Keitaro TSUCHIYA, Kazunori HAGIMOTO
  • Publication number: 20160118486
    Abstract: Semiconductor device including: silicon-based substrate; first buffer layer on silicon-based substrate and is formed of first layer containing Al composition and second layer containing less Al than the first layer, the first and second layers being alternately stacked; second buffer layer on the first buffer layer and is formed of third layer containing Al composition and fourth layer containing less Al than the third layer, the third and fourth layers being alternately stacked; and third buffer layer on the second buffer layer and is formed of fifth layer containing Al composition and sixth layer containing less Al than the fifth layer, the fifth and sixth layers being alternately stacked, wherein the second buffer layer contains more Al than the first and third buffer layers. Thus, the semiconductor device leakage can be suppressed while reducing stress which is applied to buffer layer and can improve flatness of active layer upper face.
    Type: Application
    Filed: May 2, 2014
    Publication date: April 28, 2016
    Applicants: Sanken Electric Co., Ltd., Shin-Etsu Handotai Co., Ltd.
    Inventors: Hiroshi SHIKAUCHI, Ken SATO, Hirokazu GOTO, Masaru SHINOMIYA, Keitaro TSUCHIYA, Kazunori HAGIMOTO
  • Publication number: 20160111273
    Abstract: A semiconductor substrate having a silicon-based substrate, a buffer layer provided on the silicon-based substrate and made of a nitride semiconductor containing boron, and an operation layer formed on the buffer layer, wherein a concentration of boron in the buffer layer gradually decreasing toward a side of the operation layer from a side of the silicon-based substrate. Thereby, the semiconductor substrate in which the buffer layer contains boron sufficient to obtain a dislocation suppression effect and boron is not diffused to the operation layer is provided.
    Type: Application
    Filed: May 2, 2014
    Publication date: April 21, 2016
    Applicants: SANKEN ELECTRIC CO., LTD., SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Hiroshi SHIKAUCHI, Ken SATO, Hirokazu GOTO, Masaru SHINOMIYA, Keitaro TSUCHIYA, Kazunori HAGIMOTO
  • Patent number: 9281187
    Abstract: The invention provides a method for manufacturing a nitride semiconductor device that grows a multilayer film of a III-V group nitride semiconductor in a reaction furnace into which a III group element raw material gas and a V group element raw material gas are introduced, the method including: growing a first nitride semiconductor layer at a first raw material gas flow rate of the V group element raw material gas and a first carrier gas flow rate; and growing a second nitride semiconductor layer at a second raw material gas flow rate of the V group element raw material gas lower than the first raw material gas flow rate and a second carrier gas flow rate higher than the first carrier gas flow rate, wherein the first nitride semiconductor layer and the second nitride semiconductor layer are stacked.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: March 8, 2016
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Ken Sato, Hirokazu Goto, Hiroshi Shikauchi, Keitaro Tsuchiya, Masaru Shinomiya, Kazunori Hagimoto
  • Publication number: 20150126018
    Abstract: The invention provides a method for manufacturing a nitride semiconductor device that grows a multilayer film of a III-V group nitride semiconductor in a reaction furnace into which a III group element raw material gas and a V group element raw material gas are introduced, the method including: growing a first nitride semiconductor layer at a first raw material gas flow rate of the V group element raw material gas and a first carrier gas flow rate; and growing a second nitride semiconductor layer at a second raw material gas flow rate of the V group element raw material gas lower than the first raw material gas flow rate and a second carrier gas flow rate higher than the first carrier gas flow rate, wherein the first nitride semiconductor layer and the second nitride semiconductor layer are stacked.
    Type: Application
    Filed: April 19, 2013
    Publication date: May 7, 2015
    Inventors: Ken Sato, Hirokazu Goto, Hiroshi Shikauchi, Keitaro Tsuchiya, Masaru Shinomiya, Kazunori Hagimoto
  • Publication number: 20150084163
    Abstract: The present invention provides an epitaxial substrate including a silicon substrate containing oxygen atoms in concentrations of 4×1017 cm?3 or more and 6×1017 cm?3 or less and containing boron atoms in concentrations of 5×1018 cm?3 or more and 6×1019 cm?3 or less and a semiconductor layer that is placed on the silicon substrate and is made of a material having a thermal expansion coefficient different from the thermal expansion coefficient of the silicon substrate. As a result, the epitaxial substrate in which the occurrence of warpage caused by the stress between the silicon substrate and the semiconductor layer is suppressed is provided.
    Type: Application
    Filed: April 19, 2013
    Publication date: March 26, 2015
    Inventors: Hiroshi Shikauchi, Hirokazu Goto, Ken Sato, Masaru Shinomiya, Keitaro Tsuchiya, Kazunori Hagimoto
  • Publication number: 20150028457
    Abstract: The present invention includes: a silicon-based substrate; and an epitaxial growth layer that has a configuration in which first and second nitride semiconductor layers having different lattice constants and thermal expansion coefficients are alternately laminated, and is arranged on the silicon-based substrate so that a film thickness thereof is gradually reduced at an outer edge portion. As a result, there are provided an epitaxial substrate and a semiconductor device in which generation of cracks at the outer edge portion is suppressed, and a method for manufacturing the semiconductor device.
    Type: Application
    Filed: February 14, 2013
    Publication date: January 29, 2015
    Inventors: Hiroshi Shikauchi, Hirokazu Goto, Ken Sato, Masaru Shinomiya, Keitaro Tsuchiya, Kazunori Hagimoto
  • Publication number: 20060145177
    Abstract: A light emitting device 100 of the invention is the one using a first main surface of a compound semiconductor layer portion, having a light emitting layer section 24 therein, as a light extraction surface, and having, on the second main surface side of the compound semiconductor layer, a device-substrate 7 bonded thereto while placing, in between, a main metal layer 10 having a reflective surface reflecting light from the light emitting layer section 24 towards the light extraction surface side, and is characterized in that the device-substrate 7 is composed of a Si substrate having a conductivity type of p type, and that the device-substrate 7 has, as being formed on the main surface thereof on the main metal layer 10 side, a contact layer 31 having Al as a major component.
    Type: Application
    Filed: December 19, 2003
    Publication date: July 6, 2006
    Inventors: Kazunori Hagimoto, Masato Yamada