Abstract: In a DSM including a loop in which an output signal of a quantizer is digitally processed, and fed back through a DAC to an analog filter, the quantizer quantizes an analog signal from an analog filter section to output a digital signal. The digital signal from the quantizer is digitally processed in a first-order recursive filter circuit including a variable gain amplifier and a delay element. A LUT receives both the digital signal from the quantizer and a table control signal, which is an output signal from the recursive filter circuit, and stores in advance compensation values corresponding to the both signals. A compensation value from the LUT is used to provide a digital output signal compensated for a delay. The digital output signal is converted into an analog signal in the DAC, and then subtracted from an analog input signal in the analog filter section.

Abstract: Two resistive elements and a capacitive element are coupled between a first node and each of an inverting input terminal of an operational amplifier, an output terminal of the operational amplifier, and a common node. A resistive element and a capacitive element are coupled between the first node and a signal input terminal. Two capacitive elements and a resistive element are coupled between a second node and each of the inverting input terminal, the output terminal, and the common node. Two capacitive elements are coupled between the second node and each of the signal input terminal, and the common node.

Abstract: A card connector is adapted to receive first and second electronic cards, each having a plurality of contact pads. The second card being wider than the first card. The connector includes an insulative housing with a plurality of first and second terminals mounted therein for engaging respective ones of the contact pads of the electronic cards when the cards are inserted into the connector. A cover member is pivotally mounted on the housing to permit movement of the cover member between an open position at which one of said first and second electronic cards may be inserted and a closed position at which the electronic card inserted into the cover is operatively positioned within the connector. The cover member has first and second sets of positioning members configured to position and hold electronic cards exclusively at the desired location for such card and wherein some of the positioning members of the first set also act as positioning members of the second set.

Abstract: An oversampling A/D converter includes a first filter including a first resistive element, a first capacitive element, a second resistive element, an operational amplifier, and a second capacitive element; a second filter receiving an output of the first filter; a third filter including a third resistive element, a third capacitive element, and a fourth resistive element; a quantizer receiving an output of the third filter and generating a digital signal; and a D/A converter converting the digital signal to an analog current signal. The D/A converter inputs the generated analog current signal to an inverting input terminal of the operational amplifier.

Abstract: A pipelined AD converter (1) includes a plurality of conversion stages (11, 11, . . . ). In each of the conversion stages, an analog-to-digital conversion circuit (101) converts an input voltage (Vin) from the preceding stage to a digital code (Dout). A digital-to-analog conversion circuit (102) converts the digital code obtained by the analog-to-digital conversion circuit to an intermediate voltage (Vda). A charge operation circuit (103) has: a capacitor section (C1, C2) for sampling the input voltage; and an amplifier section (104) for amplifying a mixed voltage of the input voltage sampled by the capacitor section and the intermediate voltage obtained by the digital-to-analog conversion circuit. The amplifier section (104) includes a plurality of op-amps (amp1, amp1, . . . ) having the same configuration and connected in parallel with each other.

Abstract: An integrator includes an operational amplifier, a first filter connected to an inverting input terminal of the operational amplifier, and a second filter connected between the inverting input terminal and an output terminal of the operational amplifier. The first filter includes n resistive elements connected in series, and (n?1) capacitive elements each having one end connected to an interconnecting node of the resistive elements and the other end connected to ground. The second filter includes n capacitive elements connected in series, and (n?1) resistive elements each having one end connected to an interconnecting node of the capacitive elements and the other end connected to ground.

Abstract: In a flash A/D converter, a predictor predicts next analog input data based on a digital output signal from an A/D converter, and outputs prediction data. Based on the prediction data from the predictor, a controller turns on comparators having reference voltages near the prediction data, and in order to ensure a certain degree of A/D conversion accuracy even when the prediction fails, also turns on even-numbered comparators 103.2a (where a is 0 to 7), for example. In this manner, even when prediction of next analog input data fails, a 4-bit A/D converter can perform A/D conversion with 3-bit accuracy, while saving power consumption by reducing the number of comparators to be turned on.

Abstract: A semiconductor device comprises an overflow detection circuit (5) which compares an output of at least one integrator in a ?? modulator (13) with a predetermined value to output an overflow detection signal; an overflow frequency calculation circuit (6) which calculates an overflow frequency value that is the frequency of the output from the integrator being outside a normal range, based on the overflow detection signal, and outputs the overflow frequency value; an oscillation judgment circuit (7) which judges whether the ?? modulator (13) is in the oscillation state or not based on the overflow frequency value; and an oscillation halt circuit which suppresses oscillation of the ?? modulator (13) when the oscillation judgment circuit (7) judges that the ?? modulator is in the oscillation state; wherein it is determined whether the output of the integrator is temporarily outside the normal range due to noise or the like or the output of the integrator is outside the normal range due to oscillation, by obtaini

Abstract: A successive approximation type A-to-D converter includes a cyclic D-to-A converter (11), a comparator (12) for comparing an analog value with an output value of the D-to-A converter (11), and memory means (13) for sequentially storing an output value of the comparator (12) and supplying the stored value to the D-to-A converter (11) in a reverse order.

Abstract: In a pass/fail judgment test for a semiconductor IC having plural DACs, there is a problem that the test time is undesirably increased due to an increase on the number of DACs or an increase in resolution. When testing two DACs, i.e., DAC1 and DAC2, a control unit (170) alternately increases the digital input values of the DAC1 and DAC2, whereby the output of a comparator 1 to which the analog output values of the DAC1 and DAC2 are inputted repeats inversion between “0” and “1”. It is judged whether the DACs are conforming or not by judging with a judgment unit (180) whether the output pattern of the comparator 1 matches an expected value or not.

Abstract: A successive approximation type A-to-D converter includes a cyclic D-to-A converter (11), a comparator (12) for comparing an analog value with an output value of the D-to-A converter (11), and memory means (13) for sequentially storing an output value of the comparator (12) and supplying the stored value to the D-to-A converter (11) in a reverse order.

Abstract: A successive approximation type A-to-D converter includes a cyclic D-to-A converter (11), a comparator (12) for comparing an analog value with an output value of the D-to-A converter (11), and memory means (13) for sequentially storing an output value of the comparator (12) and supplying the stored value to the D-to-A converter (11) in a reverse order.

Abstract: A pipelined AD converter (1) includes a plurality of conversion stages (11, 11, . . . ). In each of the conversion stages, an analog-to-digital conversion circuit (101) converts an input voltage (Vin) from the preceding stage to a digital code (Dout). A digital-to-analog conversion circuit (102) converts the digital code obtained by the analog-to-digital conversion circuit to an intermediate voltage (Vda). A charge operation circuit (103) has: a capacitor section (C1, C2) for sampling the input voltage; and an amplifier section (104) for amplifying a mixed voltage of the input voltage sampled by the capacitor section and the intermediate voltage obtained by the digital-to-analog conversion circuit. The amplifier section (104) includes a plurality of op-amps (amp1, amp1, . . . ) having the same configuration and connected in parallel with each other.

Abstract: A semiconductor device comprises an overflow detection circuit (5) which compares an output of at least one integrator in a ?? modulator (13) with a predetermined value to output an overflow detection signal; an overflow frequency calculation circuit (6) which calculates an overflow frequency value that is the frequency of the output from the integrator being outside a normal range, based on the overflow detection signal, and outputs the overflow frequency value; an oscillation judgment circuit (7) which judges whether the ?? modulator (13) is in the oscillation state or not based on the overflow frequency value; and an oscillation halt circuit which suppresses oscillation of the ?? modulator (13) when the oscillation judgment circuit (7) judges that the ?? modulator is in the oscillation state; wherein it is determined whether the output of the integrator is temporarily outside the normal range due to noise or the like or the output of the integrator is outside the normal range due to oscillation, by obtaini

Abstract: In a pass/fail judgment test for a semiconductor IC having plural DACs, there is a problem that the test time is undesirably increased due to an increase on the number of DACs or an increase in resolution. When testing two DACs, i.e., DAC1 and DAC2, a control unit (170) alternately increases the digital input values of the DAC1 and DAC2, whereby the output of a comparator 1 to which the analog output values of the DAC1 and DAC2 are inputted repeats inversion between “0” and “1”. It is judged whether the DACs are conforming or not by judging with a judgment unit (180) whether the output pattern of the comparator 1 matches an expected value or not.

Abstract: A successive approximation type A-to-D converter includes a cyclic D-to-A converter (11), a comparator (12) for comparing an analog value with an output value of the D-to-A converter (11), and memory means (13) for sequentially storing an output value of the comparator (12) and supplying the stored value to the D-to-A converter (11) in a reverse order.

Abstract: A high-frequency circuit device comprises a metal shield casing comprising side walls having projection parts projected innerwards and a plate-like member accommodated within the casing in contact with and fixed to the projection parts by dip-soldering. The plate-like member is either a printed circuit board having circuit elements mounted thereon or a shield plate segment for defining and shielding spaces above the printed circuit board.