Patents by Inventor Kazuo Nakazato

Kazuo Nakazato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030205771
    Abstract: A high speed/large capacity DRAM (Dynamic Random Access Memory) is generally refreshed each 0.1 sec because it loses information stored therein due to a leakage current. The DRAM also loses information stored therein upon cutoff of a power source. Meanwhile, a nonvolatile ROM (Read-only Memory) cannot be configured as a high speed/large capacity memory.
    Type: Application
    Filed: June 5, 2003
    Publication date: November 6, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Hideo Sunami, Kiyoo Itoh, Toshikazu Shimada, Kazuo Nakazato, Hiroshi Mizuta
  • Patent number: 6642574
    Abstract: A high speed/large capacity DRAM (Dynamic Random Access Memory) is generally refreshed each 0.1 sec because it loses information stored therein due to a leakage current. The DRAM also loses information stored therein upon cutoff of a power source. Meanwhile, a nonvolatile ROM (Read-only Memory) cannot be configured as a high speed/large capacity memory. A semiconductor memory device of the present invention realizes nonvolatile characteristic by shielding a drain functioning as a memory node from a leakage current by a tunnel insulator, and also realizes stable and high speed operation by adding a transistor for reading to a memory cell.
    Type: Grant
    Filed: December 4, 2000
    Date of Patent: November 4, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Hideo Sunami, Kiyoo Itoh, Toshikazu Shimada, Kazuo Nakazato, Hiroshi Mizuta
  • Publication number: 20030129001
    Abstract: Disclosed are a gain cell structure capable of making a memory cell compact in size and a method of manufacturing the same at low cost. A memory cell is constituted of a reading MIS transistor and a writing MIS transistor. The reading MIS transistor has a pair of n+ type semiconductor regions (source region and drain region) formed on a main surface of a semiconductor substrate and a first gate electrode formed on a path of the n+ type semiconductor regions 13 via a first gate insulating film. The writing MIS transistor is arranged on the reading MIS transistor and has a layered structure made by laminating a lower semiconductor layer (source region), an intermediate semiconductor layer (channel forming region), and an upper semiconductor layer (drain region) in this order. The writing MIS transistor has a vertical structure in which a second gate electrode is arranged on both sidewalls of the layered structure via a second gate insulating film.
    Type: Application
    Filed: December 30, 2002
    Publication date: July 10, 2003
    Inventors: Teruaki Kisu, Teruo Kisu, Haruko Kisu, Kazuo Nakazato, Masahito Takahashi
  • Publication number: 20030128574
    Abstract: A semiconductor integrated circuit device utilizing a memory cell containing a transistor to write information and a storage MOSFET to retain an information voltage in the gate, a word line placed to intersect with a write data line and a read data line, for connecting to the control terminal of the write transistor and a memory cell array for issuing an output on the read data line corresponding to the read signal from said memory cell in response to a select signal from said write transistor and by means of a data select circuit select one from among said plurality of read data lines from the data line select circuit and connect to either a first or second common data line, precharge said read data line to a first voltage within a first period, discharge said read data line to a second voltage by means of a second storage MOSFET of said memory cell set to on status for said word line selected within the second period, precharge said first and second common data lines to a third voltage between said first an
    Type: Application
    Filed: December 30, 2002
    Publication date: July 10, 2003
    Inventors: Kiyoo Itoh, Kazuo Nakazato
  • Publication number: 20030109102
    Abstract: A vertical MIS is provided immediately above a trench-type capacitor provided in a memory cell forming region of a semiconductor substrate, and a lateral nMIS is provided in the peripheral circuit forming region of the semiconductor substrate. After forming the capacitor, the lateral nMIS is formed. In addition, after forming the lateral nMIS, the vertical MIS is formed. Furthermore, after forming a capacitor, an isolation part of the peripheral circuit is formed.
    Type: Application
    Filed: October 24, 2002
    Publication date: June 12, 2003
    Inventors: Hiroshi Kujirai, Masahiro Moniwa, Kazuo Nakazato, Teruaki Kisu, Teruo Kisu, Teruaki Kisu, Haruko Kisu, Hideyuki Matsuoka, Tsuyoshi Tabata, Satoru Haga
  • Patent number: 6574143
    Abstract: A flash memory cell is based on a floating gate transistor design in which a floating gate is separated from a channel by a tunnel oxide. The cell is programmed and erased by electrons tunnelling on and off the floating gate through the tunnel oxide. To retain charge stored on the floating gate, the tunnel oxide is relatively thick. As a result it takes a long time, of the order of 100 &mgr;s, to program and erase the cell, Injection of charge onto the floating gate is helped by hot-electron and channel inversion effects. However, no such effects help tunnelling of charge off the floating gate, Introduction of a silicon heterostructure hot-electron diode comprising an intrinsic silicon region promotes electron transport from the floating gate during erasing cycles and so reduces the erase voltage. Furthermore, the intrinsic silicon region provides an additional barrier to charge leakage, so permitting a thinner tunnel oxide to be used and thus read/write cycles become shorter.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: June 3, 2003
    Assignee: Hitachi Europe, Ltd.
    Inventor: Kazuo Nakazato
  • Patent number: 6515892
    Abstract: A semiconductor integrated circuit device utilizing a memory cell containing a transistor to write information and a storage MOSFET to retain an information voltage in the gate, a word line placed to intersect with a write data line and a read data line, for connecting to the control terminal of the write transistor and a memory cell array for issuing an output on the read data line corresponding to the read signal from said memory cell in response to a select signal from said write transistor and by means of a data select circuit select one from among said plurality of read data lines from the data line select circuit and connect to either a first or second common data line, precharge said read data line to a first voltage within a first period, discharge said read data line to a second voltage by means of a second storage MOSFET of said memory cell set to on status for said word line selected within the second period, precharge said first and second common data lines to a third voltage between said first an
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: February 4, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Kiyoo Itoh, Kazuo Nakazato
  • Patent number: 6501116
    Abstract: Disclosed are a gain cell structure capable of making a memory cell compact in size and a method of manufacturing the same at low cost. A memory cell is constituted of a reading MIS transistor and a writing MIS transistor. The reading MIS transistor has a pair of n+ type semiconductor regions (source region and drain region) formed on a main surface of a semiconductor substrate and a first gate electrode formed on a path of the n+ type semiconductor regions 13 via a first gate insulating film. The writing MIS transistor is arranged on the reading MIS transistor and has a layered structure made by laminating a lower semiconductor layer (source region), an intermediate semiconductor layer (channel forming region), and an upper semiconductor layer (drain region) in this order. The writing MIS transistor has a vertical structure in which a second gate electrode is arranged on both sidewalls of the layered structure via a second gate insulating film.
    Type: Grant
    Filed: December 27, 2001
    Date of Patent: December 31, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Teruaki Kisu, Kazuo Nakazato, Masahito Takahashi
  • Patent number: 6465834
    Abstract: In the case of a large capacity DRAM (Dynamic Random Access Memory) of a conventional type, since a signal voltage read out from a memory cell is low, the action thereof is apt to be unstable. If a gain is added to a memory cell to obtain a large output voltage, the area for a memory cell becomes large. Accordingly, a memory cell with RAM action being stable and which requires a small area is needed. A memory cell according to the present invention is provided with MOS transistors 2, 3, 4, 5 to read out storage information, transistors 8 and 11b to write storage information, and a capacitor 11a to control the voltage at the storage node. These component parts are assembled to form a 3-dimensional structure.
    Type: Grant
    Filed: March 1, 2000
    Date of Patent: October 15, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Kazuo Nakazato, Kiyoo Ito
  • Publication number: 20020139973
    Abstract: A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.
    Type: Application
    Filed: April 15, 2002
    Publication date: October 3, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Kazuo Nakazato, Kiyoo Itoh, Hiroshi Mizuta, Toshikazu Shimada, Hideo Sunami, Tatsuya Teshima, Toshiyuki Mine, Ken Yamaguchi
  • Publication number: 20020098639
    Abstract: Disclosed are a gain cell structure capable of making a memory cell compact in size and a method of manufacturing the same at low cost. A memory cell is constituted of a reading MIS transistor and a writing MIS transistor. The reading MIS transistor has a pair of n+ type semiconductor regions (source region and drain region) formed on a main surface of a semiconductor substrate and a first gate electrode formed on a path of the n+ type semiconductor regions 13 via a first gate insulating film. The writing MIS transistor is arranged on the reading MIS transistor and has a layered structure made by laminating a lower semiconductor layer (source region), an intermediate semiconductor layer (channel forming region), and an upper semiconductor layer (drain region) in this order. The writing MIS transistor has a vertical structure in which a second gate electrode is arranged on both sidewalls of the layered structure via a second gate insulating film.
    Type: Application
    Filed: December 27, 2001
    Publication date: July 25, 2002
    Inventors: Teruaki Kisu, Kazuo Nakazato, Masahito Takahashi, Teruo Kisu, Haruko Kisu
  • Publication number: 20010013621
    Abstract: A flash memory cell is based on a floating gate transistor design in which a floating gate is separated from a channel by a tunnel oxide. The cell is programmed and erased by electrons tunnelling on and off the floating gate through the tunnel oxide. To retain charge stored on the floating gate, the tunnel oxide is relatively thick. As a result it takes a long time, of the order of 100 &mgr;s, to program and erase the cell, Injection of charge onto the floating gate is helped by hot-electron and channel inversion effects. However, no such effects help tunnelling of charge off the floating gate, Introduction of a silicon heterostructure hot-electron diode comprising an intrinsic silicon region promotes electron transport from the floating gate during erasing cycles and so reduces the erase voltage. Furthermore, the intrinsic silicon region provides an additional barrier to charge leakage, so permitting a thinner tunnel oxide to be used and thus read/write cycles become shorter.
    Type: Application
    Filed: December 8, 2000
    Publication date: August 16, 2001
    Inventor: Kazuo Nakazato
  • Publication number: 20010002054
    Abstract: A high speed/large capacity DRAM (Dynamic Random Access Memory) is generally refreshed each 0.1 sec because it loses information stored therein due to a leakage current. The DRAM also loses information stored therein upon cutoff of a power source. Meanwhile, a nonvolatile ROM (Read-only-Memory) cannot be configured as a high speed/large capacity memory.
    Type: Application
    Filed: December 4, 2000
    Publication date: May 31, 2001
    Inventors: Hideo Sunami, Kiyoo Itoh, Toshikazu Shimada, Kazuo Nakazato, Hiroshi Mizuta
  • Patent number: 6211531
    Abstract: A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.
    Type: Grant
    Filed: January 27, 2000
    Date of Patent: April 3, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Kazuo Nakazato, Kiyoo Itoh, Hiroshi Mizuta, Toshikazu Shimada, Hideo Sunami, Tatsuya Teshima, Toshiyuki Mine, Ken Yamaguchi
  • Patent number: 6169308
    Abstract: A high speed/large capacity DRAM (Dynamic Random Access Memory) is generally refreshed each 0.1 sec because it loses information stored therein due to a leakage current. The DRAM also loses information stored therein upon cutoff of a power source. Meanwhile, a nonvolatile ROM (Read-only Memory) cannot be configured as a high speed/large capacity memory. A semiconductor memory device of the present invention realizes nonvolatile characteristic by shielding a drain functioning as a memory node from a leakage current by a tunnel insulator, and also realizes stable and high speed operation by adding a transistor for reading to a memory cell.
    Type: Grant
    Filed: October 6, 1998
    Date of Patent: January 2, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Hideo Sunami, Kiyoo Itoh, Toshikazu Shimada, Kazuo Nakazato, Hiroshi Mizuta
  • Patent number: 6060723
    Abstract: A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.
    Type: Grant
    Filed: June 10, 1998
    Date of Patent: May 9, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Kazuo Nakazato, Kiyoo Itoh, Hiroshi Mizuta, Toshikazu Shimada, Hideo Sunami, Tatsuya Teshima, Toshiyuki Mine, Ken Yamaguchi
  • Patent number: 5952692
    Abstract: A memory device includes a memory node (1) to which charge is written through a tunnel barrier configuration (2) from a control electrode (9). The stored charge effects the conductivity of a source/drain path (4) and data is read by monitoring the conductivity of the path. The charge barrier configuration comprises a multiple tunnel barrier configuration, which may comprise alternating layers (16) of polysilicon of 3 nm thickness and layers (15) of Si.sub.3 N.sub.4 of 1 nm thickness, overlying polycrystalline layer of silicon (1) which forms the memory node. Alternative barrier configurations (2) are described, including a Schottky barrier configuration, and conductive nanometre scale conductive islands (30, 36, 44), which act as the memory node, distributed in an electrically insulating matrix.
    Type: Grant
    Filed: October 28, 1997
    Date of Patent: September 14, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Kazuo Nakazato, Kiyoo Itoh, Hiroshi Mizuta, Toshihiko Sato, Toshikazu Shimada, Haroon Ahmed
  • Patent number: 5677637
    Abstract: A memory device includes a memory node (2) to which is connected a tunnel barrier configuration such that the node exhibits first and second quantized memory states for which the level of stored charge is limited by Coulomb Blockade and a surplus or shortfall of a small number of electrons for example ten electrons or even a single electron can be used to represent quantized memory states. A series of the nodes N0-N3 that are interconnected by tunnel barriers D can be arranged as a logic device. Clock waveforms V1-V3 applied to clock lines C1 1-C1 3 selectively alter the probability of charge carriers passing through the tunnel diodes D from node to node. An output device, typically a Coulomb blockade electrometer provides an output logical signal indicative of the logical state of node N3. Arrays of separately addressable memory cells M.sub.mn are also described, that utilize gated multiple tunnel junctions (MTJs) as their barrier configurations.
    Type: Grant
    Filed: February 27, 1996
    Date of Patent: October 14, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Kazuo Nakazato, Haroon Ahmed, Julian D. White
  • Patent number: 5391912
    Abstract: This invention relates to a semiconductor device, in which a singlecrystal semiconductor substrate whose principal surface is (111) is etched from the principal surface thereof in the direction perpendicular thereto to form a vertical trench and a lateral trench is formed at the bottom portion of the side wall of the vertical trench by effecting an anisotropic etching with respect to crystallographical axes so that the etching proceeds in the direction of <110> axis, the lateral and the vertical trenches being filled with polycrystalline or amorphous semiconductor or insulator.
    Type: Grant
    Filed: October 20, 1992
    Date of Patent: February 21, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Masatada Horiuchi, Kazuo Nakazato
  • Patent number: 5227660
    Abstract: This invention relates to a semiconductor device, in which a singlecrystal semiconductor substrate whose principal surface is a (111) plane is etched from the principal surface thereof in the direction perpendicular thereto to form a vertical trench and a lateral trench is formed at the bottom portion of the side wall of the vertical trench by effecting an anisotropic etching with respect to crystallographical axes so that the etching proceeds in the direction of <110> axis, the lateral and the vertical trenches being filled with polycrystalline or amorphous semiconductor or insulator.
    Type: Grant
    Filed: January 29, 1991
    Date of Patent: July 13, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Masatada Horiuchi, Kazuo Nakazato