Patents by Inventor Kazuo Nakazato

Kazuo Nakazato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5177584
    Abstract: A bipolar SRAM which includes a forward bipolar transistor and a reverse bipolar transistor on an identical semiconductor substrate, is disclosed. Concretely, the base region of the reverse bipolar transistor is formed at a deeper position of the substrate than the base region of the forward bipolar transistor, thereby to heighten the cutoff frequency f.sub.T of the reverse bipolar transistor.
    Type: Grant
    Filed: January 28, 1991
    Date of Patent: January 5, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Akihisa Uchida, Yuji Yatsuda, Katsumi Ogiue, Kazuo Nakazato, Takahiro Onai
  • Patent number: 5109263
    Abstract: A vertical bipolar transistor arrangement in which the distance between the emitter and the isolation region is kept within a range determined by the sum of emitter depth and base width (i.e., the thickness of the base in the depth direction). This keeps the carriers given by the emitter from getting trapped inside, thereby preventing the cut-off frequency from dropping.
    Type: Grant
    Filed: July 24, 1990
    Date of Patent: April 28, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Mitsuo Nanba, Tohru Nakamura, Kazuo Nakazato, Takeo Shiba, Katsuyoshi Washio, Kiyoji Ikeda, Takahiro Onai, Masatada Horiuchi
  • Patent number: 5061645
    Abstract: A method of manufacturing a bipolar transistor semiconductor device wherein the active regions of a transistor are formed in an opening provided in an insulating film, electrodes are led out by a polycrystalline silicon film formed on the insulating film, and the upper surfaces of the emitter and base electrodes and the exposed surface of the insulating film are substantially even.
    Type: Grant
    Filed: March 26, 1990
    Date of Patent: October 29, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Kazuo Nakazato, Tohru Nakamura, Masatoshi Matsuda, Takao Miyazaki, Tokuo Kure, Takahiro Okabe, Minoru Nagata
  • Patent number: 4958320
    Abstract: A bipolar memory of a construction having high immunity to soft error attributable to alpha rays is provided. The transistors of a flip flop, i.e., the essential circuitry of the memory cell, are inverted and the load device thereof has shielding means for shielding the flip flop from the noise produced within the substrate. Bipolar transistors and Schottky barrier diodes are employed as the load devices. A buried layer (ordinarily, an n type layer) and a doped layer of the reverse conductivity type (ordinarily the p type) are formed in a region where the device is provided, and a reverse bias is applied across the buried layer and the doped layer to shut off the noise produced within the substrate.
    Type: Grant
    Filed: June 2, 1989
    Date of Patent: September 18, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Noriyuki Homma, Tohru Nakamura, Kazuo Nakazato, Motoaki Matsumoto, Tetsuya Hayashida, Masaharu Kubo, Kazuhiko Sagara
  • Patent number: 4956688
    Abstract: A bipolar memory of a construction having high immunity from soft error attributable to alpha rays is provided. The transistors of a flip flop, i.e., the essential circuit of the memory cell, are inverted, and the load device thereof has a shielding arrangement for shielding the flip flop from the noise produced within the substrate. Either pnp type transistors or Schottky barrier diodes are employed as the load devices. A buried layer (ordinarily, an n type layer) and a doped layer of the reverse conductivity type (ordinarily the p type) are formed in the region where the device is provided. A reverse bias is applied across the buried layer and the doped layer to shut off the noise produced within the substrate.
    Type: Grant
    Filed: June 27, 1989
    Date of Patent: September 11, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Noriyuki Honma, Tohru Nakamura, Kazuo Nakazato, Motoaki Matsumoto, Tetsuya Hayashida, Masaharu Kubo, Kazuhiko Sagara
  • Patent number: 4887145
    Abstract: A bipolar transistor capable of operating at high speeds. In a bipolar transistor designed for operation at high speeds, a polycrystalline silicon layer used as a base electrode effects is a contact area with respect to the base region which lacks precision or tends to increase. Further, when the transistor is formed in a small size, the ratio of the contact area with respect to the polycrystalline area increases, making it difficult to increase the operation speed. In order to reduce the contact area of the polycrystalline silicon layer, this invention deals with the structure in which the polycrystalline silicon layer is brought into contact with a portion near the edge of the convex semiconductor layer maintaining a small size and a high precision.
    Type: Grant
    Filed: December 3, 1986
    Date of Patent: December 12, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Katsuyoshi Washio, Tohru Nakamura, Kazuo Nakazato, Masatada Horiuchi, Tetsuya Hayashida
  • Patent number: 4860086
    Abstract: A semiconductor device is constructed so that an insulation film is provided in regions other than a protruding portion of a substrate. A polycrystalline silicon layer and a metal silicide layer are formed over said insulation film to provide a multi-layer structure, and a take-out portion for at least one of the emitter, base, and collector members of a bipolar transistor provided in the mesa region is constituted by a film of this multi-layer structure. By virtue of the use of metal silicide together with the polycrystalline silicon, a very low resistance is achieved which enhances the device's operating speed. Further, the metal silicide is separated from the protruding portion of the substrate by a portion of the polycrystalline silicon to provide a smooth interface with the substrate. This smooth interface significantly reduces crystal defects in the single crystal substrate.
    Type: Grant
    Filed: March 16, 1987
    Date of Patent: August 22, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Tohru Nakamura, Masahiko Ogirima, Kazuo Nakazato, Takao Miyazaki, Naoki Yamamoto, Minoru Nagata, Shojiro Sugaki, deceased
  • Patent number: 4858184
    Abstract: A bipolar memory of a construction having high immunity to soft error attributable to alpha rays is provided. The transistors of a flip flop, i.e., the essential circuitry of the memory cell, are inverted and the load device thereof has shielding means for shielding the flip flop from the noise produced within the substrate. Bipolar transistors and Schottky barrier diodes are employed as the load devices. A buried layer (ordinarily, an n type layer) and a doped layer of the reverse conductivity type (ordinarily the p type) are formed in a region where the device is provided, and a reverse bias is applied across the buried layer and the doped layer to shut off the noise produced within the substrate.
    Type: Grant
    Filed: April 27, 1987
    Date of Patent: August 15, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Noriyuki Homma, Tohru Nakamura, Kazuo Nakazato, Motoaki Matsumoto, Tetsuya Hayashida, Masaharu Kubo, Kazuhiko Sagara
  • Patent number: 4829361
    Abstract: A semiconductor device wherein a layer doped with impurities is provided between a buried layer and an epitaxial layer, said layer doped with impurities having a conductivity of the type opposite to that of said buried layer and said epitaxial layer, a reversely biasing voltage is applied across the buried layer and the layer doped with impurities, and side surfaces of the epitaxial layer are surrounded by an insulator.This helps effectively prevent the element formed in the epitaxial layer from being affected by .alpha.-particles and greatly improve reliability of the semiconductor device.
    Type: Grant
    Filed: November 16, 1987
    Date of Patent: May 9, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhiko Sagara, Tohru Nakamura, Kazuo Nakazato, Tokuo Kure, Kiyoji Ikeda, Noriyuki Homma
  • Patent number: 4825281
    Abstract: A semiconductor device wherein the active regions of a transistor are formed in an opening provided in an insulating film, electrodes are led out by a polycrystalline silicon film formed on the insulating film, and the upper surfaces of the emitter and base electrodes and the exposed surface of the insulating film are substantially even.
    Type: Grant
    Filed: October 21, 1982
    Date of Patent: April 25, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Kazuo Nakazato, Tohru Nakamura, Masatoshi Matsuda, Takao Miyazaki, Tokuo Kure, Takahiro Okabe, Minoru Nagata
  • Patent number: 4819055
    Abstract: The invention deals with a semiconductor device which comprises a semiconductor substrate of a first conductivity type, a semiconductor region formed on said substrate, and a first insulation film provided between said semiconductor region and said semiconductor substrate, wherein said semiconductor substrate is isolated by said insulation film from a polycrystalline silicon layer formed in the periphery of said semiconductor region thereby to reduce the parasitic capacitance, and wherein said insulation film is stretched and arranged on the lower side of said semiconductor region.
    Type: Grant
    Filed: May 2, 1988
    Date of Patent: April 4, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Kazuo Nakazato, Tohru Nakamura, Takao Miyazaki, Nobuyoshi Natsuaki, Masahiko Ogirima, Minoru Nagata
  • Patent number: 4812894
    Abstract: A semiconductor device includes a first insulation film formed on a monocrystalline substrate and having an opening, a monocrystalline semiconductor layer formed so as to protrude into the first insulation film, and a conductive layer formed in contact with the side section of the monocrystalline semiconductor layer and extending over a second insulation film formed on the monocrystalline semiconductor layer.
    Type: Grant
    Filed: May 3, 1988
    Date of Patent: March 14, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Tohru Nakamura, Kazuo Nakazato, Noriyuki Homma, Kazuhiko Sagara, Takeo Shiba, Tokuo Kure, Tetsuya Hayashida
  • Patent number: 4809828
    Abstract: A one-way damping valve mechanism in a hydraulic damper having a first hydraulic chamber defined in a cylinder, and a piston rod having an inner end on which there is mounted a piston slidably fitted in the cylinder, divides the first hydraulic chamber into a second hydraulic chamber and a third hydraulic chamber. The valve mechansim produces a damping force when the piston is moved in a prescribed direction to move working oil from the second hydraulic chamber into the third hydraulic chamber. The valve mechanism comprises a subvalve for defining a first hydraulic passage to generate a damping force when the piston moves at an extremely low speed in the prescribed direction, and a main valve for defining a second hydraulic passage to generate a damping force when the piston moves in a medium/high speed range in the prescribed direction.
    Type: Grant
    Filed: July 1, 1987
    Date of Patent: March 7, 1989
    Assignee: Kabushiki Kaisha Showa Seisakusho
    Inventor: Kazuo Nakazato
  • Patent number: 4769687
    Abstract: A lateral bipolar transistor affording a good controllability for a base length is disclosed.In fabricating a lateral bipolar transistor by forming a single crystal column and disposing heavily doped polycrystalline regions on both sides of the column, contact surfaces between the single crystal column and the heavily doped polycrystalline regions are controlled by etching of an oxide film. The etching of the oxide film can provide a device of a precision higher than attained by controlling any other element.
    Type: Grant
    Filed: April 20, 1987
    Date of Patent: September 6, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Kazuo Nakazato, Tohru Nakamura, Masataka Kato, Takahiro Okabe
  • Patent number: 4558680
    Abstract: A system for controlling the air-fuel ratio for an engine comprises a first passage for communicating a portion adjacent to an inlet of an air bleed of a carburetor of the engine with a portion of the intake passage between an air-cleaner and a supercharger, a valve provided in the first passage, an actuator comprising a diaphragm operatively connected to the valve and first and second chambers defined by the diaphragm. A second passage is provided for communicating the first chamber with the intake passage at the upstream side of the inlet of the air bleed, and a third passage is provided for communicating the second chamber with the intake passage at the downstream side of a throttle valve of the engine. The actuator is so arranged that the valve opens when the difference between pressures in the first and second chambers exceeds a predetermined value, thereby supplying rich air-fuel mixture.
    Type: Grant
    Filed: February 10, 1984
    Date of Patent: December 17, 1985
    Assignee: Fuji Jukogyo Kabushiki Kaisha
    Inventor: Kazuo Nakazato
  • Patent number: 4541384
    Abstract: A system for controlling the air-fuel ratio for an engine comprises a valve provided in an inlet of an air bleed of a carburetor of the engine. An actuator comprises a diaphragm operatively connected to the valve and first and second chambers defined by the diaphragm. An opening is provided for communicating the first chamber with the intake passage at the upstream side of a throttle valve of the engine, and a passage is provided for communicating the second chamber with the intake passage at the downstream side of the throttle valve. The actuator is so arranged that the valve closes when the difference between the pressures in the first and second chambers exceeds a predetermined value, thereby supplying a rich air-fuel mixture.
    Type: Grant
    Filed: March 5, 1984
    Date of Patent: September 17, 1985
    Assignee: Fuji Jukogyo Kabushiki Kaisha
    Inventor: Kazuo Nakazato
  • Patent number: 4476834
    Abstract: A system for controlling air-fuel ratio of air-fuel mixture for an internal combustion engine having a two-barrel carburetor. The system is provided with an O.sub.2 sensor for detecting the concentration of oxygen in the exhaust gases, an on-off electromagnetic valve for correcting the air-fuel ratio of the air-fuel mixture supplied by the carburetor and an electronic control circuit. The electronic control circuit operates to compare output signal of the detector with a stoichiometric value, and to produce driving pulses for driving the on-off electromagnetic valve and for controlling the air-fuel ratio to a value approximately equal to the stoichiometric air-fuel ratio. A fixed signal generating circuit is selectively connected to the electronic control circuit. The two-barrel carburetor has an actuator actuated by the vacuum at the venturi of the carburetor for opening a throttle valve of the secondary side of the carburetor.
    Type: Grant
    Filed: May 26, 1982
    Date of Patent: October 16, 1984
    Assignees: Fuji Jukogyo Kabushiki Kaisha, Nissan Motor Company, Limited
    Inventor: Kazuo Nakazato
  • Patent number: 4192683
    Abstract: A photographic light-sensitive material comprising a layer which contains a compound represented by the following Formula I ##STR1## wherein R.sub.1 is an alkyl group having 1 to 18 carbon atoms, R.sub.2 is a hydrogen atom or an alkyl group having 1 to 18 carbon atoms with a proviso that when R.sub.2 is a hydrogen atom, R.sub.1 is an alkyl group having 1 to 7 carbon atoms, M is a cation and n is a number of 1 to 50.
    Type: Grant
    Filed: October 18, 1977
    Date of Patent: March 11, 1980
    Assignee: Konishiroku Photo Industry Co., Ltd.
    Inventors: Eiichi Sakamoto, Masao Ishihara, Kazuo Nakazato, Hiroshi Yamada, Sadatugu Terada, Kenichi Kitahara, Naoto Abe, Mamoru Komiya, Masaru Kanbe