Patents by Inventor Kazuo Teshirogi

Kazuo Teshirogi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150132865
    Abstract: A semiconductor substrate is secured by suction to a rear face of a supporting face of a substrate supporting table. In this event, the thickness of the semiconductor substrate is made fixed by planarization on the rear face, and the rear face is forcibly brought into a state free from undulation by the suction to the supporting face, so that the rear face becomes a reference face for planarization of a front face. In this state, a tool is used to cut surface layers of Au projections and a resist mask on the front face, thereby planarizing the Au projections and the resist mask so that their surfaces become continuously flat. This can planarize the surfaces of fine bumps formed on the substrate at a low cost and a high speed in place of CMP.
    Type: Application
    Filed: January 20, 2015
    Publication date: May 14, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Masataka Mizukoshi, Yoshiharu Ishizuki, Kanae Nakagawa, Keishiro Okamoto, Kazuo Teshirogi, Taiji Sakai
  • Patent number: 9010615
    Abstract: To provide a bonding apparatus capable of increasing product quality by realizing high-precision control of a pressing force applied upon mounting of an electronic component on a substrate by bonding, and to a bonding method capable of providing high-quality products stably. The bonding apparatus includes: at least a bonding head 100 for pressing an electronic component 6 against a substrate 1 to bond it to the substrate 1; a plurality of load detection mechanisms (e.g., load sensors 5) substantially equally spaced so as to face one another under a substrate stage S supporting the substrate 1 provided with the electronic component 6; and a pressure detection unit 20 for detecting pressing force at the bonding surface between the electronic component 6 and substrate 1 on the basis of the pressure values detected by the individual load detection mechanisms 5.
    Type: Grant
    Filed: April 10, 2014
    Date of Patent: April 21, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kazuhiro Yoshimoto, Yuzo Shimobeppu, Kazuo Teshirogi, Yoshiaki Shinjo
  • Patent number: 8962470
    Abstract: A semiconductor substrate is secured by suction to a rear face of a supporting face of a substrate supporting table. In this event, the thickness of the semiconductor substrate is made fixed by planarization on the rear face, and the rear face is forcibly brought into a state free from undulation by the suction to the supporting face, so that the rear face becomes a reference face for planarization of a front face. In this state, a tool is used to cut surface layers of Au projections and a resist mask on the front face, thereby planarizing the Au projections and the resist mask so that their surfaces become continuously flat. This can planarize the surfaces of fine bumps formed on the substrate at a low cost and a high speed in place of CMP.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: February 24, 2015
    Assignee: Fujitsu Limited
    Inventors: Masataka Mizukoshi, Yoshikatsu Ishizuki, Kanae Nakagawa, Keishiro Okamoto, Kazuo Teshirogi, Taiji Sakai
  • Publication number: 20140217153
    Abstract: To provide a bonding apparatus capable of increasing product quality by realizing high-precision control of a pressing force applied upon mounting of an electronic component on a substrate by bonding, and to a bonding method capable of providing high-quality products stably. The bonding apparatus includes: at least a bonding head 100 for pressing an electronic component 6 against a substrate 1 to bond it to the substrate 1; a plurality of load detection mechanisms (e.g., load sensors 5) substantially equally spaced so as to face one another under a substrate stage S supporting the substrate 1 provided with the electronic component 6; and a pressure detection unit 20 for detecting pressing force at the bonding surface between the electronic component 6 and substrate 1 on the basis of the pressure values detected by the individual load detection mechanisms 5.
    Type: Application
    Filed: April 10, 2014
    Publication date: August 7, 2014
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Kazuhiro Yoshimoto, Yuzo Shimobeppu, Kazuo Teshirogi, Yoshiaki Shinjo
  • Patent number: 8444799
    Abstract: A method for manufacturing a semiconductor device includes adhering an adhesive layer of a surface protective tape including a base material film, an intermediate layer disposed on the base material film, and the adhesive layer disposed on the intermediate layer to one surface of a semiconductor substrate; curing the intermediate layer while a flat plate is pressed against the base material film of the surface protective tape; grinding the other surface of the semiconductor substrate; curing the adhesive layer; and separating the surface protective tape from the semiconductor substrate.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: May 21, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hironori Fukaya, Yuzo Shimobeppu, Kazuhiro Yoshimoto, Kazuo Teshirogi, Kazuyuki Uragou, Mika Sakamoto, Masaya Tazawa
  • Patent number: 8440545
    Abstract: A method of manufacturing a semiconductor device includes spraying fluid onto a surface of a treatment target substrate including a semiconductor substrate; forming a protection layer on the surface of the treatment target substrate after spraying the fluid; selectively removing the protection layer and a part of the treatment target substrate by an energy beam; and conducting removal processing on an area of the treatment target substrate from which the protection layer and the part of the treatment target substrate are selectively removed.
    Type: Grant
    Filed: November 18, 2008
    Date of Patent: May 14, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hironori Fukaya, Yuzo Shimobeppu, Kazuhiro Yoshimoto, Yoshiaki Shinjo, Kazuo Teshirogi, Mika Sakamoto
  • Patent number: 8016973
    Abstract: A film bonding method of bonding a die bond film without causing any breakage. The die bond film is pressed against a wafer having a surface protective tape bonded thereto using a film-setting roller and a film-bonding roller, and a laser beam having a predetermined shape is irradiated to an area between the rollers. While rotationally moving the film-setting roller and the film-bonding roller, the laser beam is scanned on the wafer in accordance with their motion, and a portion of the die bond film, melted by the laser beam, is pressed against the wafer by the film-bonding roller following the film-setting roller to bond the die bond film to the wafer. Since the die bond film is bonded to the wafer by melting the same by the laser beam, even if the wafer is thin and reduced in its strength, it is possible to avoid the wafer from being damaged e.g. by thermal contraction of the surface protective tape.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: September 13, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Yoshiaki Shinjo, Yuzo Shimobeppu, Kazuo Teshirogi, Kazuhiro Yoshimoto
  • Publication number: 20110048615
    Abstract: A method for manufacturing a semiconductor device includes adhering an adhesive layer of a surface protective tape including a base material film, an intermediate layer disposed on the base material film, and the adhesive layer disposed on the intermediate layer to one surface of a semiconductor substrate; curing the intermediate layer while a flat plate is pressed against the base material film of the surface protective tape; grinding the other surface of the semiconductor substrate; curing the adhesive layer; and separating the surface protective tape from the semiconductor substrate.
    Type: Application
    Filed: September 2, 2010
    Publication date: March 3, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Hironori Fukaya, Yuzo Shimobeppu, Kazuhiro Yoshimoto, Kazuo Teshirogi, Kazuyuki Uragou, Mika Sakamoto, Masaya Tazawa
  • Publication number: 20110011919
    Abstract: To provide a bonding apparatus capable of increasing product quality by realizing high-precision control of a pressing force applied upon mounting of an electronic component on a substrate by bonding, and to a bonding method capable of providing high-quality products stably. The bonding apparatus includes: at least a bonding head 100 for pressing an electronic component 6 against a substrate 1 to bond it to the substrate 1; a plurality of load detection mechanisms (e.g., load sensors 5) substantially equally spaced so as to face one another under a substrate stage S supporting the substrate 1 provided with the electronic component 6; and a pressure detection unit 20 for detecting pressing force at the bonding surface between the electronic component 6 and substrate 1 on the basis of the pressure values detected by the individual load detection mechanisms 5.
    Type: Application
    Filed: September 23, 2010
    Publication date: January 20, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Kazuhiro Yoshimoto, Yuzo Shimobeppu, Kazuo Teshirogi, Yoshiaki Shinjo
  • Patent number: 7857140
    Abstract: A semiconductor wafer storage case is disclosed that includes plural support members that are spaced at predetermined intervals with respect to each other and are each configured to come into contact with a peripheral edge region of a first face of a semiconductor wafer, and an elastic member that elastically supports the support members with respect to each other and is configured to elastically deform to come into contact with a second face of the semiconductor wafer and press the semiconductor wafer onto a corresponding support member.
    Type: Grant
    Filed: June 2, 2008
    Date of Patent: December 28, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Yoshiaki Shinjo, Yuzo Shimobeppu, Kazuo Teshirogi, Kazuhiro Yoshimoto
  • Patent number: 7820487
    Abstract: A manufacturing method of a semiconductor device includes providing an adhesive on a supporting board, the supporting board being where a semiconductor element is to be mounted; providing a member configured to block flow of the adhesive on a first main surface of the semiconductor element, the semiconductor element having a second main surface where an outside connection terminal is provided; mounting the semiconductor element on a part of the supporting board where the adhesive is provided by pressing the semiconductor element via the member.
    Type: Grant
    Filed: March 20, 2009
    Date of Patent: October 26, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kazuo Teshirogi, Yuzo Shimobeppu, Kazuhiro Yoshimoto, Yoshiaki Shinjo
  • Patent number: 7704856
    Abstract: A substrate support (201) having a flat supporting surface (201a) is prepared, and a semiconductor substrate (1) is fixed to the substrate supporting surface (201) by attaching a wiring forming surface (1a) to the supporting surface (201a) by suction, for example, by vacuum suction. On this occasion, the wiring forming surface (1a) is forcibly flattened by being attached to the supporting surface (201a) by suction, and therefore the wiring forming surface (1a) becomes a reference plane for planarization of a back surface (1b). In this state, planarization processing is performed by mechanically grinding the back surface (1b) to grind away projecting portions (12) of the back surface (1b). Hence, variations in the thickness of the substrate (especially, semiconductor substrate) are made uniform, and high-speed planarization is realized easily and inexpensively without disadvantages such as dishing and without any limitation on a wiring design.
    Type: Grant
    Filed: March 23, 2007
    Date of Patent: April 27, 2010
    Assignee: Fujitsu Limited
    Inventors: Kanae Nakagawa, Masataka Mizukoshi, Kazuo Teshirogi
  • Patent number: 7655505
    Abstract: A manufacturing method of a semiconductor device, includes i) a step of providing a transparent member above a main surface of a semiconductor substrate where a plurality of semiconductor elements is formed; ii) a first dividing step of dividing the transparent member corresponding to a designated area of the semiconductor element; iii) a second dividing step of dividing the transparent member corresponding to an external configuration of the semiconductor element; and iv) a dividing step of dividing the semiconductor substrate into the semiconductor elements corresponding to a dividing position of the transparent member.
    Type: Grant
    Filed: May 22, 2006
    Date of Patent: February 2, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Kazuo Teshirogi, Yuzo Shimobeppu, Kazuhiro Yoshimoto, Yoshiaki Shinjo
  • Patent number: 7648907
    Abstract: A substrate support (201) having a flat supporting surface (201a) is prepared, and a semiconductor substrate (1) is fixed to the substrate supporting surface (201) by attaching a wiring forming surface (1a) to the supporting surface (201a) by suction, for example, by vacuum suction. On this occasion, the wiring forming surface (1a) is forcibly flattened by being attached to the supporting surface (201a) by suction, and therefore the wiring forming surface (1a) becomes a reference plane for planarization of a back surface (1b). In this state, planarization processing is performed by mechanically grinding the back surface (1b) to grind away projecting portions (12) of the back surface (1b). Hence, variations in the thickness of the substrate (especially, semiconductor substrate) are made uniform, and high-speed planarization is realized easily and inexpensively without disadvantages such as dishing and without any limitation on a wiring design.
    Type: Grant
    Filed: March 23, 2007
    Date of Patent: January 19, 2010
    Assignee: Fujitsu Limited
    Inventors: Kanae Nakagawa, Masataka Mizukoshi, Kazuo Teshirogi
  • Publication number: 20090239355
    Abstract: A method of manufacturing a semiconductor device includes spraying fluid onto a surface of a treatment target substrate including a semiconductor substrate; forming a protection layer on the surface of the treatment target substrate after spraying the fluid; selectively removing the protection layer and a part of the treatment target substrate by an energy beam; and conducting removal processing on an area of the treatment target substrate from which the protection layer and the part of the treatment target substrate are selectively removed.
    Type: Application
    Filed: November 18, 2008
    Publication date: September 24, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Hironori FUKAYA, Yuzo SHIMOBEPPU, Kazuhiro YOSHIMOTO, Yoshiaki SHINJO, Kazuo TESHIROGI, Mika SAKAMOTO
  • Patent number: 7571538
    Abstract: The present invention relates to a Jig and method of manufacturing a semiconductor substrate including the back grind step, the dicing step, the pick up step, and the die bonding step of the wafer; and to a semiconductor substrate jig used in such method. The object of the present invention is to mitigate the effect and to prevent damage caused by the lack of strength in thinned semiconductor substrates. A jig with an outer frame 21, and a rubber film 22 arranged within the outer frame 21 and having increasing and decreasing body size while deforming its shape by supplying air therein are provided. As the volume of the rubber film 22 increases, the wafer-fixing jig 20 deforms the rubber film and allows the tapes 2 and 6 arranged between the wafer 1 and the rubber film 22A to be pushed toward the wafer 1 gradually from the center outward. The attachment step, the back grind step, the tape reapplication step, the pick up step and the die bonding step are conducted using such wafer-fixing jig.
    Type: Grant
    Filed: March 10, 2005
    Date of Patent: August 11, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Kazuo Teshirogi, Yuzo Shimobeppu, Kazuhiro Yoshimoto, Mitsuhisa Watanabe, Yoshiaki Shinjo, Eiji Yoshida, Noboru Hayasaka
  • Publication number: 20090186451
    Abstract: A manufacturing method of a semiconductor device includes providing an adhesive on a supporting board, the supporting board being where a semiconductor element is to be mounted; providing a member configured to block flow of the adhesive on a first main surface of the semiconductor element, the semiconductor element having a second main surface where an outside connection terminal is provided; mounting the semiconductor element on a part of the supporting board where the adhesive is provided by pressing the semiconductor element via the member.
    Type: Application
    Filed: March 20, 2009
    Publication date: July 23, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Kazuo TESHIROGI, Yuzo SHIMOBEPPU, Kazuhiro YOSHIMOTO, Yoshiaki SHINJO
  • Publication number: 20090186425
    Abstract: A semiconductor substrate (1) is secured by suction to a rear face (1b) of a supporting face (11a) of a substrate supporting table (11). In this event, the thickness of the semiconductor substrate (1) is made fixed by planarization on the rear face (1b), and the rear face (1b) is forcibly brought into a state free from undulation by the suction to the supporting face (11a), so that the rear face (1b) becomes a reference face for planarization of a front face (1a). In this state, a tool (10) is used to cut surface layers of Au projections (2) and a resist mask (12) on the front face (1a), thereby planarizing the Au projections (2) and the resist mask (12) so that their surfaces become continuously flat. This can planarize the surfaces of fine bumps formed on the substrate at a low cost and a high speed in place of CMP.
    Type: Application
    Filed: March 30, 2009
    Publication date: July 23, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Masataka MIZUKOSHI, Yoshikatsu ISHIZUKI, Kanae NAKAGAWA, Keishiro OKAMOTO, Kazuo TESHIROGI, Taiji SAKAI
  • Patent number: 7563343
    Abstract: In a film lamination apparatus and method, there is no one-side contact of a pressing roller that presses a film to be laminated. The film is laminated using a rotatable pressing roller having a heater incorporated therein. The pressing roller is pressed onto the film placed on a semiconductor substrate while generating heat by the heater inside the pressing roller. The pressing roller is rolled on the film so as to laminate the film on the semiconductor substrate by partially heating the film by the pressing roller while moving the pressing roller.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: July 21, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Kazuo Teshirogi, Yuzo Shimobeppu, Yoshiaki Shinjo
  • Patent number: 7485962
    Abstract: A substrate support (201) having a flat supporting surface (201a) is prepared, and a semiconductor substrate (1) is fixed to the substrate supporting surface (201) by attaching a wiring forming surface (1a) to the supporting surface (201a) by suction, for example, by vacuum suction. On this occasion, the wiring forming surface (1a) is forcibly flattened by being attached to the supporting surface (201a) by suction, and therefore the wiring forming surface (1a) becomes a reference plane for planarization of a back surface (1b). In this state, planarization processing is performed by mechanically grinding the back surface (1b) to grind away projecting portions (12) of the back surface (1b). Hence, variations in the thickness of the substrate (especially, semiconductor substrate) are made uniform, and high-speed planarization is realized easily and inexpensively without disadvantages such as dishing and without any limitation on a wiring design.
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: February 3, 2009
    Assignee: Fujitsu Limited
    Inventors: Kanae Nakagawa, Masataka Mizukoshi, Kazuo Teshirogi