Patents by Inventor Kazuo Teshirogi

Kazuo Teshirogi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6824643
    Abstract: In a semiconductor device manufacturing process, a semiconductor wafer is diced into a plurality of semiconductor chips, which are then peeled, from a dicing tape, using a peeling device. The peeling device includes a plurality of annular contact members arranged one after another from the outside to the inside, and the annular contact members are operated so that the semiconductor chip is successively peeled from the tape from the outer circumferential portion thereof toward the central portion thereof.
    Type: Grant
    Filed: March 4, 2002
    Date of Patent: November 30, 2004
    Assignee: Fujitsu Limited
    Inventors: Kazuhiro Yoshimoto, Kazuo Teshirogi, Eiji Yoshida
  • Publication number: 20040161882
    Abstract: The present invention relates to a method of manufacturing a semiconductor substrate including the back grind step, the dicing step, the pick up step, and the die bonding step of the wafer; and to a semiconductor substrate jig used in such method. The object of the present invention is to mitigate the effect and to prevent damage caused by the lack of strength in thinned semiconductor substrates. A jig with an outer frame 21, and a rubber film 22 arranged within the outer frame 21 and having increasing and decreasing body size while deforming its shape by supplying air therein are provided. As the volume of the rubber film 22 increases, the wafer-fixing jig 20 deforms the rubber film and allows the tapes 2 and 6 arranged between the wafer 1 and the rubber film 22A to be pushed toward the wafer 1 gradually from the center outward. The attachment step, the back grind step, the tape reapplication step, the pick up step and the die bonding step are conducted using such wafer-fixing jig.
    Type: Application
    Filed: February 6, 2004
    Publication date: August 19, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Kazuo TESHIROGI, Yuzo SHIMOBEPPU, Kazuhiro YOSHIMOTO, Mitsuhisa WATANABE, Yoshiaki SHINJO, Eiji YOSHIDA, Noboru HAYASAKA
  • Patent number: 6750074
    Abstract: The present invention relates to a method of manufacturing a semiconductor substrate including the back grind step, the dicing step, the pick up step, and the die bonding step of the wafer; and to a semiconductor substrate jig used in such method. The object of the present invention is to mitigate the effect and to prevent damage caused by the lack of strength in thinned semiconductor substrates. A jig with an outer frame 21, and a rubber film 22 arranged within the outer frame 21 and having increasing and decreasing body size while deforming its shape by supplying air therein are provided. As the volume of the rubber film 22 increases, the wafer-fixing jig 20 deforms the rubber film and allows the tapes 2 and 6 arranged between the wafer 1 and the rubber film 22A to be pushed toward the wafer 1 gradually from the center outward. The attachment step, the back grind step, the tape reapplication step, the pick up step and the die bonding step are conducted using such wafer-fixing jig.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: June 15, 2004
    Assignee: Fujitsu Limited
    Inventors: Kazuo Teshirogi, Yuzo Shimobeppu, Kazuhiro Yoshimoto, Mitsuhisa Watanabe, Yoshiaki Shinjo, Eiji Yoshida, Noboru Hayasaka
  • Publication number: 20040106301
    Abstract: In a film lamination apparatus and method, there is no one-side contact of a pressing roller that presses a film to be laminated. The film is laminated using a rotatable pressing roller having a heater incorporated therein. The pressing roller is pressed onto the film placed on a semiconductor substrate while generating heat by the heater inside the pressing roller. The pressing roller is rolled on the film so as to laminate the film on the semiconductor substrate by partially heating the film by the pressing roller while moving the pressing roller.
    Type: Application
    Filed: November 24, 2003
    Publication date: June 3, 2004
    Applicant: FUJITSU LIMITED,
    Inventors: Kazuo Teshirogi, Yuzo Shimobeppu, Yoshiaki Shinjo
  • Publication number: 20030077880
    Abstract: A method of making a semiconductor device includes a back-grinding step of grinding a back surface of a semiconductor substrate, a dicing step of dicing the semiconductor substrate along predetermined dicing lines so as to make pieces of semiconductor devices after the back-grinding step, and a laser exposure step of shining laser light on the back surface of the semiconductor substrate after the back-grinding step so as to remove grinding marks generated by the back-grinding step.
    Type: Application
    Filed: March 20, 2002
    Publication date: April 24, 2003
    Applicant: Fujitsu Limited
    Inventors: Yoshiaki Shinjo, Yuzo Shimobeppu, Kazuo Teshirogi, Kazuhiro Yoshimoto, Eiji Yoshida, Noboru Hayasaka, Mitsuhisa Watanabe
  • Publication number: 20030075271
    Abstract: In a semiconductor device manufacturing process, a semiconductor wafer is diced into a plurality of semiconductor chips, which are then peeled, from a dicing tape, using a peeling device. The peeling device includes a plurality of annular contact members arranged one after another from the outside to the inside, and the annular contact members are operated so that the semiconductor chip is successively peeled from the tape from the outer circumferential portion thereof toward the central portion thereof.
    Type: Application
    Filed: March 4, 2002
    Publication date: April 24, 2003
    Applicant: Fujitsu Limited
    Inventors: Kazuhiro Yoshimoto, Kazuo Teshirogi, Eiji Yoshida
  • Publication number: 20030077993
    Abstract: Disclosed is a flat-object holder for holding a flat object-and-frame assembly, which has the flat object fixed to the frame with a protection tape. The flat-object holder comprises at least a flat object supporting area for fixedly holding the flat object via the protection tape by applying a suction force, and a frame fixing area for fastening the frame. The flat-object holder bearing the flat object-and-frame assembly can be fixedly held by a selected chuck table by applying a negative pressure to the flat object supporting area. The flat-object holder can transfer and put the flat object-and-frame assembly in a container. Thus, no matter how thin the flat object may be, it can be handled without the fear of breaking.
    Type: Application
    Filed: July 31, 2002
    Publication date: April 24, 2003
    Inventors: Yuzo Shimobeppu, Kazuo Teshirogi, Kazuhiro Yoshimoto, Mitsuhisa Watanabe, Yoshiaki Shinjo, Takashi Mori, Koichi Yajima, Yusuke Kimura
  • Publication number: 20030077854
    Abstract: The present invention relates to a method of manufacturing a semiconductor substrate including the back grind step, the dicing step, the pick up step, and the die bonding step of the wafer; and to a semiconductor substrate jig used in such method. The object of the present invention is to mitigate the effect and to prevent damage caused by the lack of strength in thinned semiconductor substrates. A jig with an outer frame 21, and a rubber film 22 arranged within the outer frame 21 and having increasing and decreasing body size while deforming its shape by supplying air therein are provided. As the volume of the rubber film 22 increases, the wafer-fixing jig 20 deforms the rubber film and allows the tapes 2 and 6 arranged between the wafer 1 and the rubber film 22A to be pushed toward the wafer 1 gradually from the center outward. The attachment step, the back grind step, the tape reapplication step, the pick up step and the die bonding step are conducted using such wafer-fixing jig.
    Type: Application
    Filed: March 20, 2002
    Publication date: April 24, 2003
    Applicant: Fujitsu Limited
    Inventors: Kazuo Teshirogi, Yuzo Shimobeppu, Kazuhiro Yoshimoto, Mitsuhisa Watanabe, Yoshiaki Shinjo, Eiji Yoshida, Noboru Hayasaka
  • Patent number: 6528348
    Abstract: A plurality of semiconductor devices can be mounted on a mounting board in a three-dimensional structure by stacking one on another with a simple structure. A semiconductor element is mounted on a first surface of an interposer. Electrode pads connected to the semiconductor element are arranged around the semiconductor element on the first surface of the interposer. Protruding electrodes are provided on the respective electrode pads. Through holes are formed in the interposer so as to extend from a second surface opposite to the first surface of the redistribution substrate to the respective electrode pads. The semiconductor element is encapsulated by a seal resin. Each of the protruding electrodes is higher than the sealed portion of the semiconductor element.
    Type: Grant
    Filed: February 19, 2002
    Date of Patent: March 4, 2003
    Assignee: Fujitsu Limited
    Inventors: Fumihiko Ando, Akira Takashima, Hiroshi Onodera, Eiji Yoshida, Kazuo Teshirogi
  • Patent number: 6461942
    Abstract: Semiconductor chips are formed on a wafer. The wafer is diced, while a dicing tape applied to the wafer is kept intact. Each of the semiconductor chips is fixed by suction and then removed from the dicing tape. Each of the semiconductor chips is unfixed by ceasing the suction and picked up and conveyed.
    Type: Grant
    Filed: December 26, 2000
    Date of Patent: October 8, 2002
    Assignee: Fujitsu Limited
    Inventors: Mitsuhisa Watanabe, Kazuo Teshirogi, Eiji Yoshida, Yuzo Shimobeppu, Yoshito Konno, Kyouhei Tamaki
  • Publication number: 20020074630
    Abstract: A plurality of semiconductor devices can be mounted on a mounting board in a three-dimensional structure by stacking one on another with a simple structure. A semiconductor element is mounted on a first surface of an interposer. Electrode pads connected to the semiconductor element are arranged around the semiconductor element on the first surface of the interposer. Protruding electrodes are provided on the respective electrode pads. Through holes are formed in the interposer so as to extend from a second surface opposite to the first surface of the redistribution substrate to the respective electrode pads. The semiconductor element is encapsulated by a seal resin. Each of the protruding electrodes is higher than the sealed portion of the semiconductor element.
    Type: Application
    Filed: February 19, 2002
    Publication date: June 20, 2002
    Applicant: FUJITSU LIMITED
    Inventors: Fumihiko Ando, Akira Takashima, Hiroshi Onodera, Eiji Yoshida, Kazuo Teshirogi
  • Patent number: 6388333
    Abstract: A plurality of semiconductor devices can be mounted on a mounting board in a three-dimensional structure by stacking one on another with a simple structure. A semiconductor element is mounted on a first surface of an interposer. Electrode pads connected to the semiconductor element are arranged around the semiconductor element on the first surface of the interposer. Protruding electrodes are provided on the respective electrode pads. Through holes are formed in the interposer so as to extend from a second surface opposite to the first surface of the redistribution substrate to the respective electrode pads. The semiconductor element is encapsulated by a seal resin. Each of the protruding electrodes is higher than the sealed portion of the semiconductor element.
    Type: Grant
    Filed: June 27, 2000
    Date of Patent: May 14, 2002
    Assignee: Fujitsu Limited
    Inventors: Fumihiko Taniguchi, Kouhei Orikawa, Tadashi Uno, Fumihiko Ando, Akira Takashima, Hiroshi Onodera, Eiji Yoshida, Kazuo Teshirogi
  • Publication number: 20010049160
    Abstract: Semiconductor chips are formed on a wafer. The wafer is diced, while a dicing tape applied to the wafer is kept intact. Each of the semiconductor chips is fixed by suction and then removed from the dicing tape. Each of the semiconductor chips is unfixed by ceasing the suction and picked up and conveyed.
    Type: Application
    Filed: December 26, 2000
    Publication date: December 6, 2001
    Applicant: FUJITSU LIMITED
    Inventors: Mitsuhisa Watanabe, Kazuo Teshirogi, Eiji Yoshida, Yuzo Shimobeppu, Yoshito Konno, Kyouhei Tamaki