Patents by Inventor Kazuo Teshirogi
Kazuo Teshirogi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7479627Abstract: A semiconductor device, includes a semiconductor substrate having a main surface where a light receiving element area is formed; a projection part provided in the periphery of the light receiving element area on the main surface of the semiconductor substrate; an adhesive material layer provided in the external periphery of the projection part on the main surface of the semiconductor substrate; and a transparent plate supported by the projection part and fixed above the light receiving element area by the adhesive material layer.Type: GrantFiled: April 24, 2006Date of Patent: January 20, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Kazuhiro Yoshimoto, Yuzo Shimobeppu, Kazuo Teshirogi, Yoshiaki Shinjo
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Patent number: 7432114Abstract: To provide a low-cost, efficient semiconductor device manufacturing method for connecting electrodes of a pair of bases (e.g., a pair of a semiconductor chip and a circuit board, or a pair of semiconductor chips) together in a short time. The method of the present invention includes: forming magnetic bumps 34 on at least one of first and second bases 10A and 40 to be bonded together at their corresponding electrodes (e.g., electrodes 15 and electrodes 41); aligning the electrodes 15 of the first base 10A to positions corresponding to the electrodes 41 of the second base 40 for connection, by means of magnetic forces of the magnetic bumps 34 formed over the first base 10A; and connecting the electrodes 15 of the first base 10A to the electrodes 41 of the second base 40, wherein the alignment is made for a plurality of the first bases 10A at a time.Type: GrantFiled: September 6, 2006Date of Patent: October 7, 2008Assignee: Fujitsu LimitedInventors: Kazuo Teshirogi, Yuzo Shimobeppu, Kazuhiro Yoshimoto, Yoshiaki Shinjo, Masataka Mizukoshi
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Publication number: 20080230438Abstract: A semiconductor wafer storage case is disclosed that includes plural support members that are spaced at predetermined intervals with respect to each other and are each configured to come into contact with a peripheral edge region of a first face of a semiconductor wafer, and an elastic member that elastically supports the support members with respect to each other and is configured to elastically deform to come into contact with a second face of the semiconductor wafer and press the semiconductor wafer onto a corresponding support member.Type: ApplicationFiled: June 2, 2008Publication date: September 25, 2008Applicant: FUJITSU LIMITEDInventors: Yoshiaki SHINJO, Yuzo SHIMOBEPPU, Kazuo TESHIROGI, Kazuhiro YOSHIMOTO
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Patent number: 7395847Abstract: The present invention relates to a method of manufacturing a semiconductor substrate including the back grind step, the dicing step, the pick up step, and the die bonding step of the wafer; and to a semiconductor substrate jig used in such method. The object of the present invention is to mitigate the effect and to prevent damage caused by the lack of strength in thinned semiconductor substrates. A jig with an outer frame 21, and a rubber film 22 arranged within the outer frame 21 and having increasing and decreasing body size while deforming its shape by supplying air therein are provided. As the volume of the rubber film 22 increases, the wafer-fixing jig 20 deforms the rubber film and allows the tapes 2 and 6 arranged between the wafer 1 and the rubber film 22A to be pushed toward the wafer 1 gradually from the center outward. The attachment step, the back grind step, the tape reapplication step, the pick up step and the die bonding step are conducted using such wafer-fixing jig.Type: GrantFiled: March 10, 2005Date of Patent: July 8, 2008Assignee: Fujitsu LimitedInventors: Kazuo Teshirogi, Yuzo Shimobeppu, Kazuhiro Yoshimoto, Mitsuhisa Watanabe, Yoshiaki Shinjo, Eiji Yoshida, Noboru Hayasaka
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Publication number: 20070287282Abstract: A substrate support (201) having a flat supporting surface (201a) is prepared, and a semiconductor substrate (1) is fixed to the substrate supporting surface (201) by attaching a wiring forming surface (1a) to the supporting surface (201a) by suction, for example, by vacuum suction. On this occasion, the wiring forming surface (1a) is forcibly flattened by being attached to the supporting surface (201a) by suction, and therefore the wiring forming surface (1a) becomes a reference plane for planarization of a back surface (1b). In this state, planarization processing is performed by mechanically grinding the back surface (1b) to grind away projecting portions (12) of the back surface (1b). Hence, variations in the thickness of the substrate (especially, semiconductor substrate) are made uniform, and high-speed planarization is realized easily and inexpensively without disadvantages such as dishing and without any limitation on a wiring design.Type: ApplicationFiled: March 23, 2007Publication date: December 13, 2007Applicant: FUJITSU LIMITEDInventors: Kanae Nakagawa, Masataka Mizukoshi, Kazuo Teshirogi
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Publication number: 20070231961Abstract: To provide a low-cost, efficient semiconductor device manufacturing method for connecting electrodes of a pair of bases (e.g., a pair of a semiconductor chip and a circuit board, or a pair of semiconductor chips) together in a short time. The method of the present invention includes: forming magnetic bumps 34 on at least one of first and second bases 10A and 40 to be bonded together at their corresponding electrodes (e.g., electrodes 15 and electrodes 41); aligning the electrodes 15 of the first base 10A to positions corresponding to the electrodes 41 of the second base 40 for connection, by means of magnetic forces of the magnetic bumps 34 formed over the first base 10A; and connecting the electrodes 15 of the first base 10A to the electrodes 41 of the second base 40, wherein the alignment is made for a plurality of the first bases 10A at a time.Type: ApplicationFiled: September 6, 2006Publication date: October 4, 2007Applicant: FUJITSU LIMITEDInventors: Kazuo Teshirogi, Yuzo Shimobeppu, Kazuhiro Yoshimoto, Yoshiaki Shinjo, Masataka Mizukoshi
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Publication number: 20070215673Abstract: To provide a bonding apparatus capable of increasing product quality by realizing high-precision control of a pressing force applied upon mounting of an electronic component on a substrate by bonding, and to a bonding method capable of providing high-quality products stably. The bonding apparatus includes: at least a bonding head 100 for pressing an electronic component 6 against a substrate 1 to bond it to the substrate 1; a plurality of load detection mechanisms (e.g., load sensors 5) substantially equally spaced so as to face one another under a substrate stage S supporting the substrate 1 provided with the electronic component 6; and a pressure detection unit 20 for detecting pressing force at the bonding surface between the electronic component 6 and substrate 1 on the basis of the pressure values detected by the individual load detection mechanisms 5.Type: ApplicationFiled: August 15, 2006Publication date: September 20, 2007Applicant: FUJITSU LIMITEDInventors: Kazuhiro Yoshimoto, Yuzo Shimobeppu, Kazuo Teshirogi, Yoshiaki Shinjo
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Publication number: 20070196954Abstract: A manufacturing method of a semiconductor device, includes i) a step of providing a transparent member above a main surface of a semiconductor substrate where a plurality of semiconductor elements is formed; ii) a first dividing step of dividing the transparent member corresponding to a designated area of the semiconductor element; iii) a second dividing step of dividing the transparent member corresponding to an external configuration of the semiconductor element; and iv) a dividing step of dividing the semiconductor substrate into the semiconductor elements corresponding to a dividing position of the transparent member.Type: ApplicationFiled: May 22, 2006Publication date: August 23, 2007Applicant: FUJITSU LIMITEDInventors: Kazuo Teshirogi, Yuzo Shimobeppu, Kazuhiro Yoshimoto, Yoshiaki Shinjo
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Publication number: 20070196588Abstract: A film bonding method of bonding a die bond film without causing any breakage. The die bond film is pressed against a wafer having a surface protective tape bonded thereto using a film-setting roller and a film-bonding roller, and a laser beam having a predetermined shape is irradiated to an area between the rollers. While rotationally moving the film-setting roller and the film-bonding roller, the laser beam is scanned on the wafer in accordance with their motion, and a portion of the die bond film, melted by the laser beam, is pressed against the wafer by the film-bonding roller following the film-setting roller to bond the die bond film to the wafer. Since the die bond film is bonded to the wafer by melting the same by the laser beam, even if the wafer is thin and reduced in its strength, it is possible to avoid the wafer from being damaged e.g. by thermal contraction of the surface protective tape.Type: ApplicationFiled: June 28, 2006Publication date: August 23, 2007Applicant: FUJITSU LIMITEDInventors: Yoshiaki Shinjo, Yuzo Shimobeppu, Kazuo Teshirogi, Kazuhiro Yoshimoto
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Publication number: 20070184646Abstract: A substrate support (201) having a flat supporting surface (201a) is prepared, and a semiconductor substrate (1) is fixed to the substrate supporting surface (201) by attaching a wiring forming surface (1a) to the supporting surface (201a) by suction, for example, by vacuum suction. On this occasion, the wiring forming surface (1a) is forcibly flattened by being attached to the supporting surface (201a) by suction, and therefore the wiring forming surface (1a) becomes a reference plane for planarization of a back surface (1b). In this state, planarization processing is performed by mechanically grinding the back surface (1b) to grind away projecting portions (12) of the back surface (1b). Hence, variations in the thickness of the substrate (especially, semiconductor substrate) are made uniform, and high-speed planarization is realized easily and inexpensively without disadvantages such as dishing and without any limitation on a wiring design.Type: ApplicationFiled: March 23, 2007Publication date: August 9, 2007Applicant: FUJITSU LIMITEDInventors: Kanae Nakagawa, Masataka Mizukoshi, Kazuo Teshirogi
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Publication number: 20070181792Abstract: A semiconductor device, includes a semiconductor substrate having a main surface where a light receiving element area is formed; a projection part provided in the periphery of the light receiving element area on the main surface of the semiconductor substrate; an adhesive material layer provided in the external periphery of the projection part on the main surface of the semiconductor substrate; and a transparent plate supported by the projection part and fixed above the light receiving element area by the adhesive material layer.Type: ApplicationFiled: April 24, 2006Publication date: August 9, 2007Applicant: FUJITSU LIMITEDInventors: Kazuhiro Yoshimoto, Yuzo Shimobeppu, Kazuo Teshirogi, Yoshiaki Shinjo
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Patent number: 7109561Abstract: The present invention relates to a method of manufacturing a semiconductor substrate including the back grind step, the dicing step, the pick up step, and the die bonding step of the wafer; and to a semiconductor substrate jig used in such method. The object of the present invention is to mitigate the effect and to prevent damage caused by the lack of strength in thinned semiconductor substrates. A jig with an outer frame 21, and a rubber film 22 arranged within the outer frame 21 and having increasing and decreasing body size while deforming its shape by supplying air therein are provided. As the volume of the rubber film 22 increases, the wafer-fixing jig 20 deforms the rubber film and allows the tapes 2 and 6 arranged between the wafer 1 and the rubber film 22A to be pushed toward the wafer 1 gradually from the center outward. The attachment step, the back grind step, the tape reapplication step, the pick up step and the die bonding step are conducted using such wafer-fixing jig.Type: GrantFiled: March 10, 2005Date of Patent: September 19, 2006Assignee: Fujitsu LimitedInventors: Kazuo Teshirogi, Yuzo Shimobeppu, Kazuhiro Yoshimoto, Mitsuhisa Watanabe, Yoshiaki Shinjo, Eiji Yoshida, Noboru Hayasaka
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Publication number: 20050221588Abstract: The present invention relates to a method of manufacturing a semiconductor substrate including the back grind step, the dicing step, the pick up step, and the die bonding step of the wafer; and to a semiconductor substrate jig used in such method. The object of the present invention is to mitigate the effect and to prevent damage caused by the lack of strength in thinned semiconductor substrates. A jig with an outer frame 21, and a rubber film 22 arranged within the outer frame 21 and having increasing and decreasing body size while deforming its shape by supplying air therein are provided. As the volume of the rubber film 22 increases, the wafer-fixing jig 20 deforms the rubber film and allows the tapes 2 and 6 arranged between the wafer 1 and the rubber film 22A to be pushed toward the wafer 1 gradually from the center outward. The attachment step, the back grind step, the tape reapplication step, the pick up step and the die bonding step are conducted using such wafer-fixing jig.Type: ApplicationFiled: March 10, 2005Publication date: October 6, 2005Applicant: FUJITSU LIMITEDInventors: Kazuo Teshirogi, Yuzo Shimobeppu, Kazuhiro Yoshimoto, Mitsuhisa Watanabe, Yoshiaki Shinjo, Eiji Yoshida, Noboru Hayasaka
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Publication number: 20050221587Abstract: The present invention relates to a method of manufacturing a semiconductor substrate including the back grind step, the dicing step, the pick up step, and the die bonding step of the wafer; and to a semiconductor substrate jig used in such method. The object of the present invention is to mitigate the effect and to prevent damage caused by the lack of strength in thinned semiconductor substrates. A jig with an outer frame 21, and a rubber film 22 arranged within the outer frame 21 and having increasing and decreasing body size while deforming its shape by supplying air therein are provided. As the volume of the rubber film 22 increases, the wafer-fixing jig 20 deforms the rubber film and allows the tapes 2 and 6 arranged between the wafer 1 and the rubber film 22A to be pushed toward the wafer 1 gradually from the center outward. The attachment step, the back grind step, the tape reapplication step, the pick up step and the die bonding step are conducted using such wafer-fixing jig.Type: ApplicationFiled: March 10, 2005Publication date: October 6, 2005Applicant: FUJITSU LIMITEDInventors: Kazuo Teshirogi, Yuzo Shimobeppu, Kazuhiro Yoshimoto, Mitsuhisa Watanabe, Yoshiaki Shinjo, Eiji Yoshida, Noboru Hayasaka
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Publication number: 20050221589Abstract: The present invention relates to a method of manufacturing a semiconductor substrate including the back grind step, the dicing step, the pick up step, and the die bonding step of the wafer; and to a semiconductor substrate jig used in such method. The object of the present invention is to mitigate the effect and to prevent damage caused by the lack of strength in thinned semiconductor substrates. A jig with an outer frame 21, and a rubber film 22 arranged within the outer frame 21 and having increasing and decreasing body size while deforming its shape by supplying air therein are provided. As the volume of the rubber film 22 increases, the wafer-fixing jig 20 deforms the rubber film and allows the tapes 2 and 6 arranged between the wafer 1 and the rubber film 22A to be pushed toward the wafer 1 gradually from the center outward. The attachment step, the back grind step, the tape reapplication step, the pick up step and the die bonding step are conducted using such wafer-fixing jig.Type: ApplicationFiled: March 10, 2005Publication date: October 6, 2005Applicant: FUJITSU LIMITEDInventors: Kazuo Teshirogi, Yuzo Shimobeppu, Kazuhiro Yoshimoto, Mitsuhisa Watanabe, Yoshiaki Shinjo, Eiji Yoshida, Noboru Hayasaka
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Patent number: 6951800Abstract: A method of making a semiconductor device includes a back-grinding step of grinding a back surface of a semiconductor substrate, a dicing step of dicing the semiconductor substrate along predetermined dicing lines so as to make pieces of semiconductor devices after the back-grinding step, and a laser exposure step of shining laser light on the back surface of the semiconductor substrate after the back-grinding step so as to remove grinding marks generated by the back-grinding step.Type: GrantFiled: March 20, 2002Date of Patent: October 4, 2005Assignee: Fujitsu LimitedInventors: Yoshiaki Shinjo, Yuzo Shimobeppu, Kazuo Teshirogi, Kazuhiro Yoshimoto, Eiji Yoshida, Noboru Hayasaka, Mitsuhisa Watanabe
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Publication number: 20050170640Abstract: A substrate support (201) having a flat supporting surface (201a) is prepared, and a semiconductor substrate (1) is fixed to the substrate supporting surface (201) by attaching a wiring forming surface (1a) to the supporting surface (201a) by suction, for example, by vacuum suction. On this occasion, the wiring forming surface (1a) is forcibly flattened by being attached to the supporting surface (201a) by suction, and therefore the wiring forming surface (1a) becomes a reference plane for planarization of a back surface (1b). In this state, planarization processing is performed by mechanically grinding the back surface (1b) to grind away projecting portions (12) of the back surface (1b). Hence, variations in the thickness of the substrate (especially, semiconductor substrate) are made uniform, and high-speed planarization is realized easily and inexpensively without disadvantages such as dishing and without any limitation on a wiring design.Type: ApplicationFiled: April 1, 2005Publication date: August 4, 2005Applicant: FUJITSU LIMITEDInventors: Kanae Nakagawa, Masataka Mizukoshi, Kazuo Teshirogi
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Publication number: 20050161814Abstract: A semiconductor substrate (1) is secured by suction to a rear face (1b) of a supporting face (11a) of a substrate supporting table (11). In this event, the thickness of the semiconductor substrate (1) is made fixed by planarization on the rear face (1b), and the rear face (1b) is forcibly brought into a state free from undulation by the suction to the supporting face (11a), so that the rear face (1b) becomes a reference face for planarization of a front face (1a). In this state, a tool (10) is used to cut surface layers of Au projections (2) and a resist mask (12) on the front face (1a), thereby planarizing the Au projections (2) and the resist mask (12) so that their surfaces become continuously flat. This can planarize the surfaces of fine bumps formed on the substrate at a low cost and a high speed in place of CMP.Type: ApplicationFiled: March 21, 2005Publication date: July 28, 2005Applicant: FUJITSU LIMITEDInventors: Masataka Mizukoshi, Yoshikatsu Ishizuki, Kanae Nakagawa, Keishiro Okamoto, Kazuo Teshirogi, Taiji Sakai
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Patent number: 6902944Abstract: The present invention relates to a method of manufacturing a semiconductor substrate including the back grind step, the dicing step, the pick up step, and the die bonding step of the wafer; and to a semiconductor substrate jig used in such method. The object of the present invention is to mitigate the effect and to prevent damage caused by the lack of strength in thinned semiconductor substrates. A jig with an outer frame 21, and a rubber film 22 arranged within the outer frame 21 and having increasing and decreasing body size while deforming its shape by supplying air therein are provided. As the volume of the rubber film 22 increases, the wafer-fixing jig 20 deforms the rubber film and allows the tapes 2 and 6 arranged between the wafer 1 and the rubber film 22A to be pushed toward the wafer 1 gradually from the center outward. The attachment step, the back grind step, the tape reapplication step, the pick up step and the die bonding step are conducted using such wafer-fixing jig.Type: GrantFiled: February 6, 2004Date of Patent: June 7, 2005Assignee: Fujitsu LimitedInventors: Kazuo Teshirogi, Yuzo Shimobeppu, Kazuhiro Yoshimoto, Mitsuhisa Watanabe, Yoshiaki Shinjo, Eiji Yoshida, Noboru Hayasaka
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Publication number: 20050085171Abstract: A flat-object holder can hold a flat object-and-frame assembly, and the holder has the flat object fixed to the frame with protection tape. The flat-object holder includes at least a flat object supporting area for fixedly holding the flat object via the protection tape by applying a suction force, and a frame fixing area for fastening the frame. The flat-object holder bearing the flat object-and-frame assembly can be fixedly held by a selected chuck table by applying a negative pressure to the flat object supporting area. The flat-object holder can transfer and put the flat object-and-frame assembly in a container. Thus, no matter how thin the flat object may be, it can be handled without the fear of breaking.Type: ApplicationFiled: November 12, 2004Publication date: April 21, 2005Inventors: Yuzo Shimobeppu, Kazuo Teshirogi, Kazuhiro Yoshimoto, Mitsuhisa Watanabe, Yoshiaki Shinjo, Takashi Mori, Koichi Yajima, Yusuke Kimura