Abstract: Disclosed is a glass fiber-reinforced crystalline resin composition superior in the surface properties and the mechanical properties of a molded article thereof. Specifically, provided is a glass fiber-reinforced crystalline resin composition containing a glass fiber sizing agent that is an aqueous resin containing an o-sulfobenzimide compound, a crystalline resin, glass fibers, wherein the glass fibers have been treated with the glass fiber sizing agent. An aqueous polyurethane resin is preferred as the aqueous resin.

Abstract: Disclosed is a glass fiber-reinforced crystalline resin composition superior in the surface properties and the mechanical properties of a molded article thereof. Specifically, provided is a glass fiber-reinforced crystalline resin composition containing a glass fiber sizing agent that is an aqueous resin containing an o-sulfobenzimide compound, a crystalline resin, glass fibers, wherein the glass fibers have been treated with the glass fiber sizing agent. An aqueous polyurethane resin is preferred as the aqueous resin.

Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

Abstract: A surfactant composition has good emulsifiability for monomer(s), and can provide a polymer emulsion (herein after simply called “the emulsion”) of good stability while decreasing coagulations of polymer particles in the emulsion. The surfactant composition contains the following components (A) and (B): (A) a reactive surfactant containing at least one polymerizable double-bond group and at least one ionic group in a molecule, and (B) a nitrogen compound insoluble or slightly soluble in ethanol. A weight ratio (A:B) of the component (A) to the component (B) is from 100:0.03 to 100:1.0.

Abstract: To provide a photosensitive composition with which partition walls (black matrix) having high sensitivity to light and being excellent in liquid repellency, and pixels excellent in the uniformity in the ink layer thickness, can be formed. A photosensitive composition, which comprises a fluoropolymer (A) having a side chain containing a group such as —(CF2)6F and a side chain containing an ethylenic double bond in one molecule, an alkali soluble photosensitive resin (B), a photopolymerization initiator (C), a black pigment (D), a polymer dispersing agent (E) having basic functional groups, and fine particles (F) other than the black pigment (D).

Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween.

Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween.

Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

Abstract: A surfactant composition has good emulsifiability for monomer(s), and can provide a polymer emulsion (herein after simply called “the emulsion”) of good stability while decreasing coagulations of polymer particles in the emulsion. The surfactant composition contains the following components (A) and (B): (A) a reactive surfactant containing at least one polymerizable double-bond group and at least one ionic group in a molecule, and (B) a nitrogen compound insoluble or slightly soluble in ethanol. A weight ratio (A:B) of the component (A) to the component (B) is from 100:0.03 to 100:1.0.

Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

Abstract: Disclosed are surfactants represented by the following formula (1): wherein R1 represents a branched aliphatic hydrocarbon group, a secondary aliphatic hydrocarbon group or a branched aliphatic acyl group, AO and AO? each independently represents an oxyalkylene group having 2 to 4 carbon atoms, L represents a group represented by formula (2) to be described below, z stands for a number of from 1 to 10, X represents a hydrogen atom or an ionic hydrophilic group, m stands for a number of from 0 to 1,000, and n stands for a number of from 0 to 1,000. wherein R2 and R3 each independently represents a hydrogen atom or a methyl group, x stands for a number of from 0 to 12, and y stands for a number of 0 or 1. These surfactants do not contain any phenyl ether group considered to have significant effects on the environment, such as a nonylphenyl group, and have performance comparable with reactive surfactants containing one or more phenyl ether groups.

Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

Abstract: An information processing apparatus is provided which is capable of carrying out the higher memory access. The information processing apparatus includes a memory unit of a synchronous DRAM device which serves to output data synchronously with the supplied clock signal, and a control unit for controlling the access to the memory unit in accordance with an instruction issued from a CPU. The clock signal which is to be supplied to the memory unit is outputted from the control unit. The clock signal which has been outputted from the control unit is supplied to the memory unit and also is pulled back to the control unit. The control unit fetches therein the data, which has been outputted from the storage unit, at the timing which is determined on the basis of the pulled back clock signal. As a result, the control unit reduces the difference between a delay of the data which is outputted from the control unit and a delay of the clock signal which is used to determine the timing at which the data is fetched therein.

Abstract: An apparatus for information display for displaying not only periodic information in accordance with schedule, but also non-periodic information regardless of the schedule, to passengers and passersby in stations, airports, harbors, bus terminals and streets, and the like. The apparatus comprises an information-storing section for storing a plurality of non-periodic information to be displayed regardless of the schedule, an input circuit for receiving a plurality of input signals transmitted from an external device or a remote place and display control section for simultaneously displaying the non-periodic information and periodic information which correspond to the kind of an input signal, when the apparatus receives this input signal from the external apparatus or the remote place. The apparatus may be a multi-screen display type having a plurality of screens.