Abstract: An apparatus for information display for displaying not only periodic information in accordance with schedule, but also non-periodic information regardless of the schedule, to passengers and passersby in stations, airports, harbors, bus terminals and streets, and the like. The apparatus comprises an information-storing section for storing a plurality of non-periodic information to be displayed regardless of the schedule, an input circuit for receiving a plurality of input signals transmitted from an external device or a remote place and display control section for simultaneously displaying the non-periodic information and periodic information which correspond to the kind of an input signal, when the apparatus receives this input signal from the external apparatus or the remote place. The apparatus may be a multi-screen display type having a plurality of screens.

Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

Abstract: An information processing apparatus is provided which is capable of carrying out the higher memory access. The information processing apparatus includes a memory unit of a synchronous DRAM device which serves to output data synchronously with the supplied clock signal, and a control unit for controlling the access to the memory unit in accordance with an instruction issued from a CPU. The clock signal which is to be supplied to the memory unit is outputted from the control unit. The clock signal which has been outputted from the control unit is supplied to the memory unit and also is pulled back to the control unit. The control unit fetches therein the data, which has been outputted from the storage unit, at the timing which is determined on the basis of the pulled back clock signal. As a result, the control unit reduces the difference between a delay of the data which is outputted from the control unit and a delay of the clock signal which is used to determine the timing at which the data is fetched therein.

Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

Abstract: An information processing apparatus is provided which is capable of carrying out the higher memory access. The information processing apparatus includes a memory unit of a synchronous DRAM device which serves to output data synchronously with the supplied clock signal, and a control unit for controlling the access to the memory unit in accordance with an instruction issued from a CPU. The clock signal which is to be supplied to the memory unit is outputted from the control unit. The clock signal which has been outputted from the control unit is supplied to the memory unit and also is pulled back to the control unit. The control unit fetches therein the data, which has been outputted from the storage unit, at the timing which is determined on the basis of the pulled back clock signal. As a result, the control unit reduces the difference between a delay of the data which is outputted from the control unit and a delay of the clock signal which is used to determine the timing at which the data is fetched therein.

Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and controL buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controlling connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

Abstract: An information processing apparatus is provided which is capable of carrying out the higher memory access. The information processing apparatus includes a memory unit of a synchronous DRAM device which serves to output data synchronously with the supplied clock signal, and a control unit for controlling the access to the memory unit in accordance with an instruction issued from a CPU. The clock signal which is to be supplied to the memory unit is outputted from the control unit. The clock signal which has been outputted from the control unit is supplied to the memory unit and also is pulled back to the control unit. The control unit fetches therein the data, which has been outputted from the storage unit, at the timing which is determined on the basis of the pulled back clock signal. As a result, the control unit reduces the difference between a delay of the data which is outputted from the control unit and a delay of the clock signal which is used to determine the timing at which the data is fetched therein.

Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

Abstract: In a computer system having an address converter for DMA (direct memory access), an address conversion apparatus in which a memory area to be accessed by the DMA can be accessed at high speed from a CPU. A "DMA address conversion area" is defined in a memory space, and address conversion means in the mode of accessing the DMA address conversion area is so constructed that, when the area has been accessed from the CPU, a physical address is generated in accordance with the address conversion routine of the DMA address conversion means or converter, so as to access a main storage. The memory area to be accessed by the DMA can be quickly accessed from the CPU without requiring such an operation as especially accessing the control ware of the address converter or producing the physical address under the management of a program run on the CPU.

Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

Abstract: An information processing apparatus is provided which is capable of carrying out the higher memory access. The information processing apparatus includes a memory unit of a synchronous DRAM device which serves to output data synchronously with the supplied clock signal, and a control unit for controlling the access to the memory unit in accordance with an instruction issued from a CPU. The clock signal which is to be supplied to the memory unit is outputted from the control unit. The clock signal which has been outputted from the control unit is supplied to the memory unit and also is pulled back to the control unit. The control unit fetches therein the data, which has been outputted from the storage unit, at the timing which is determined on the basis of the pulled back clock signal. As a result, the control unit reduces the difference between a delay of the data which is outputted from the control unit and a delay of the clock signal which is used to determine the timing at which the data is fetched therein.

Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

Abstract: An information processing system includes a central processing unit, a main storage, a main storage controller for controlling the main storage, a cache memory having a content of at least one part of addresses stored in the main storage, at least one DMA controller which is capable of referring to the main storage and a DMA address translation unit for translating a logical address outputted from the DMA controller into a physical address for referring to the main storage. The DMA address translation unit has a flag representing whether or not the cache memory is referred to on DMA. The main storage controller performs either of reference to the cache memory or direct reference to the main storage based upon the flag on DMA.

Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

Abstract: A cache memory system for controlling a cache memory. The cache memory system is connected to a central processing unit and a main memory and the cache memory system is controlled to operate in a copyback operation mode. The cache memory system includes the cache memory which operates as cache memory to the central processing unit and a control circuit, responsive to detection of an error in the cache memory, for suspending an updating operation of an entry in the cache memory in which the error was detected, controlling access to valid entries in the cache memory, and causing the cache memory to operate as cache memory only when access from the central processing unit hits the valid entries of the cache memory.

Abstract: An interruption control device for controlling interruption requests in a multiprocessor system having a plurality of processor elements and a plurality of peripheral devices. The interruption control device is connected between the processor elements and the peripheral devices. The interruption control device includes a plurality of interruption request registers for indicating the occurrence of an interruption request from either a processor element or a peripheral device to a processor element and a plurality of interruption enable registers for authorizing an interruption request of a processor element. The interruption request registers are read by the processor element being interrupted to identify the source of the interruption request.