Abstract: A bus system for an information processing system in which data transfer among plurality of modules is controlled on a common bus. In response to a bus use request from a module, a command is issued for aborting data transfer being performed by another module having a lower priority. The module which is transferring the data responds to the abort command by issuing a signal indicating that a word being transferred is the final word. The data is transferred between a master and a slave through an address bus having a same width as the data in synchronism with a clock supplied from a bus controller.

Abstract: A working system for an aeroplane comprising a hangar for accommodating the aeroplane, a partition wall provided within the hangar for partitioning the hangar into a fuselage work area around a fuselage of the aeroplane and a main wing work area around a main wing, and working tables arranged in the fuselage work area. The partition wall is movable between a predetermined partitioning position and a retracted position allowing entrance and exit of the aeroplane. The working tables are movable within the fuselage work area separately from the partition wall.

Abstract: A plurality of process requests generated from processing units, for example, direct memory access (DMA) channels are controlled by a preference circuit in accordance with a priority level assigned to each of the processing unit. An information of the highest priority obtained processing unit and its priority level is stored in latches. Another process requests having the same priority level as the stored processing unit are inhibited from being supplied to the preference circuit, so that the first generated process request is accepted and executed prior to acceptance of the another process requests having the same priority level.

Abstract: A cleaning system for use in treatment of excess paint is disclosed. The system includes a work area for cleaning excess paint by trapping the paint in a cleaning liquid, a collecting gutter being provided in a floor of said work area for introducing the cleaning liquid containing the excess paint in the form of paint sludge. The collecting gutter incorporates a filter for filtering the cleaning liquid introduced into this gutter. The system further includes a collecting device for collecting the paint sludge trapped by the filter.

Abstract: An address bus control apparatus links a memory bus connected with a CPU and a memory unit and a system bus connected with input/output units. The address bus width of the system bus is smaller than that of the memory bus and one of the input/output units is a master unit using address data of a smaller width than the address bus width of the system bus for accessing another unit. The address bus control apparatus, when bus identifying information from a master unit identifies the memory bus, delivers first complementary address data together with address data from the master unit onto the memory bus and, when the bus identifying information identifies the system bus, delivers second complementary address data onto the system bus, and thereby secures necessary address data width for each bus.

Abstract: An air conditioning system for use in an aeroplane hangar. The hangar includes a fuselage work area for works on a fuselage of an aeroplane and a main-wing work area for works on a main wing of the aeroplane, with the work areas being partitioned by a partition wall. An air conditioning device is provided for conditioning temperature of air to be fed to either work area. Further, a recycling device is provided for cleaning air exhausted from the one area and then feeding the cleaned air to the other area.

Abstract: Two arithmetic logic units (ALUs) are provided, one a high-order side and another on a low-order side such that data on the high-order side and on low-order side, output from each of a source data register and a destination data register, are respectively supplied to the ALUs to be operated on thereby. There is provided a selector circuit on the output side of the source data register, which selector circuit operates to deliver the data on the high-order side and that on the low-order side from the source data register selectively to the ALU on the high-order side and that on the low-order side according to the operating mode. Carry outputs from each of the ALUs are input to a first selector and one is selected according to the operating mode and stored in a carry flag register.