Abstract: An object of the present invention is to provide a vehicle safety assistance system enabling perception of a state of passengers. A vehicle safety assistance system according to the present invention assists safety of at least one passenger on board a vehicle, and includes: a monitoring unit capable of monitoring the passenger in the vehicle; a recognition unit recognizing a state of the passenger by monitoring information from the monitoring unit; and a control unit carrying out control of operation of the vehicle or notification to the passenger on basis of recognition information from the recognition unit, in which the monitoring unit includes a monitoring camera.

Abstract: A database management system includes: a hierarchical database including one primary database, an intermediate database, and end databases; and a searching unit which searches, from registered data in the hierarchical database, for matching data which matches a search criterion. At least the end databases store plural pieces of the registered data. The primary database or the intermediate database includes a virtual data table in which search paths are grouped by common information relating to the plural pieces of the registered data. The search paths lead to the registered data stored in: a next-lower database; or the intermediate database or the end database, each being indirectly connected to the primary database or the intermediate database through the next-lower database. The searching unit adopts, as a starting point of a search, the intermediate database or the end database which involves the common information contained in the search criterion.

Abstract: A database management system according to one embodiment includes at least one processor configured to control a hierarchical database including a plurality of end databases and a primary database directly or indirectly connected to the plurality of end databases. Each of the plurality of end databases stores sensor data. The primary database provides a virtual data table. The at least one processor transmits, to the end database, a search instruction for obtaining a result set containing a combination of an intermediate result based on the sensor data and a path ID for uniquely identifying a path connecting the primary database and the end database, receives a result set, and represents a search result based on the result set by the virtual data table and outputs the search result.

Abstract: A database management system according to one embodiment includes at least one processor configured to control a hierarchical database including a plurality of end databases and a primary database directly or indirectly connected to the plurality of end databases. Each of the plurality of end databases stores sensor data. The primary database provides a virtual data table. The at least one processor transmits, to the end database, a search instruction for obtaining a result set containing a combination of an intermediate result based on the sensor data and a path ID for uniquely identifying a path connecting the primary database and the end database, receives a result set, and represents a search result based on the result set by the virtual data table and outputs the search result.

Abstract: An ePLX unit includes a logic unit having an SRAM and a MUX, and a switch unit having an SRAM and a TG for establishing wiring connection in the logic unit. When a composite module is set in the first mode, an Add/Flag control unit uses the SRAMs as a data field and a flag field, respectively, to autonomously control the read address of each of the data field and the flag field in accordance with a control flag stored in the flag field. Furthermore, when the composite module is set in the second mode, the Add/Flag control unit writes configuration information into each of the SRAMs to reconfigure a logic circuit. Consequently, the granularity of the circuit configuration can be rendered variable, which allows improvement in flexibility when configuring a function.

Abstract: By using a fact that a bit error in an on-chip embedded memory occurs at a random address, means for creating a chip-unique ID and utilizing this ID are provided. A controller having received a verification request from outside instructs a variable power supply circuit to decrease a voltage supplied to a memory to be lower than that at the normal operation time. When the voltage supplied to the memory is stabilized, the controller requests a memory test to a memory BIST. By using an address where an error occurs due to a result of the memory test, the controller creates the chip-unique ID and uses the ID as a response to the verification request.

Abstract: A pair of operator cells each having a series-coupled circuit of first and second transistors is used as a storage unit. To-be-retrieved data and retrieval data are respectively stored in the first and second transistors, and mutually complementary data items are stored in the operator cells of the storage unit. The operator cells supply currents according to the result of an AND operation between the stored data items to corresponding bit lines, and the read data from the storage unit corresponds to the result of an EXOR operation between the retrieval data and the to-be-retrieved data. The currents flowing in the corresponding bit lines are amplified with sense amplifier circuits to drive local match lines. In the individual sub-blocks of an operator cell array, data items having different pattern lengths can be stored. The potentials of the local match lines are selected according to the data pattern lengths, and match retrieval is performed for the data items having the different pattern lengths.

Abstract: A unit operator cell includes a plurality of SOI (Silicon on Insulator) transistors, write data is stored in a body region of at least two SOI transistors, and the storage SOI transistors are connected in series with each other to a read port or each of the storage SOI transistors is singly connected to the read port. Therefore, an AND operation result or a NOT operation result of data stored in the unit operator cells can be obtained, and operation processing can be performed only by writing and reading data. A semiconductor signal processing device that can perform logic operation processing and arithmetic operation processing at high speed is implemented with low power consumption and a small occupation area.

Abstract: The present invention aims at providing a semiconductor memory device that can be manufactured by a MOS process and can realize a stable operation. A storage transistor has impurity diffusion regions, a channel formation region, a charge accumulation node, a gate oxide film, and a gate electrode. The gate electrode is connected to a gate line and the impurity diffusion region is connected to a source line. The storage transistor creates a state where holes are accumulated in the charge accumulation node and a state where the holes are not accumulated in the charge accumulation node to thereby store data “1” and data “0”, respectively. An access transistor has impurity diffusion regions, a channel formation region, a gate oxide film, and a gate electrode. The impurity diffusion region is connected to a bit line.

Abstract: A unit operator cell includes a plurality of SOI (Silicon on Insulator) transistors, write data is stored in a body region of at least two SOI transistors, and the storage SOI transistors are connected in series with each other to a read port or each of the storage SOI transistors is singly connected to the read port. Therefore, an AND operation result or a NOT operation result of data stored in the unit operator cells can be obtained, and operation processing can be performed only by writing and reading data. A semiconductor signal processing device that can perform logic operation processing and arithmetic operation processing at high speed is implemented with low power consumption and a small occupation area.

Abstract: In a content addressable memory device, before search operations in two TCAM cells connected to first and second match lines, respectively, a memory controller connects the first match line to a power source and connects the second match line to a ground, and then connects the first and second match lines to each other so as that electric potentials of the first and second match lines are the same as each other.

Abstract: An ePLX unit includes a logic unit having an SRAM and a MUX, and a switch unit having an SRAM and a TG for establishing wiring connection in the logic unit. When a composite module is set in the first mode, an Add/Flag control unit uses the SRAMs as a data field and a flag field, respectively, to autonomously control the read address of each of the data field and the flag field in accordance with a control flag stored in the flag field. Furthermore, when the composite module is set in the second mode, the Add/Flag control unit writes configuration information into each of the SRAMs to reconfigure a logic circuit. Consequently, the granularity of the circuit configuration can be rendered variable, which allows improvement in flexibility when configuring a function.

Abstract: A unit operator cell includes a plurality of SOI (Silicon on Insulator) transistors, write data is stored in a body region of at least two SOI transistors, and the storage SOI transistors are connected in series with each other to a read port or each of the storage SOI transistors is singly connected to the read port. Therefore, an AND operation result or a NOT operation result of data stored in the unit operator cells can be obtained, and operation processing can be performed only by writing and reading data. A semiconductor signal processing device that can perform logic operation processing and arithmetic operation processing at high speed is implemented with low power consumption and a small occupation area.

Abstract: By using a fact that a bit error in an on-chip embedded memory occurs at a random address, means for creating a chip-unique ID and utilizing this ID are provided. A controller having received a verification request from outside instructs a variable power supply circuit to decrease a voltage supplied to a memory to be lower than that at the normal operation time. When the voltage supplied to the memory is stabilized, the controller requests a memory test to a memory BIST. By using an address where an error occurs due to a result of the memory test, the controller creates the chip-unique ID and uses the ID as a response to the verification request.

Abstract: An ePLX unit includes a logic unit having an SRAM and a MUX, and a switch unit having an SRAM and a TG for establishing wiring connection in the logic unit. When a composite module is set in the first mode, an Add/Flag control unit uses the SRAMs as a data field and a flag field, respectively, to autonomously control the read address of each of the data field and the flag field in accordance with a control flag stored in the flag field. Furthermore, when the composite module is set in the second mode, the Add/Flag control unit writes configuration information into each of the SRAMs to reconfigure a logic circuit. Consequently, the granularity of the circuit configuration can be rendered variable, which allows improvement in flexibility when configuring a function.

Abstract: A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width.

Abstract: A CAM (Content Addressable Memory) cell includes first and second data storage portions storing data, horizontal port write gates for storing data applied through a match line pair in the data storage portions in a data write through a horizontal port, and search/read gates for driving the match lines of the match line pair in accordance with the data stored in the data storage portions in a search operation and in a data read through the horizontal port. The match lines are used as horizontal bit line pair, or signal lines for accessing the horizontal port. As the first and second data storage portions are used, it becomes possible to store ternary data, and accordingly, a write mask function of inhibiting a data write at a destination of data transfer is realized. Further, as the CAM cell is used, an arithmetic/logic operation following a search process can be executed selectively, and high speed data writing/reading becomes possible.

Abstract: The present invention aims at providing a semiconductor memory device that can be manufactured by a MOS process and can realize a stable operation. A storage transistor has impurity diffusion regions, a channel formation region, a charge accumulation node, a gate oxide film, and a gate electrode. The gate electrode is connected to a gate line and the impurity diffusion region is connected to a source line. The storage transistor creates a state where holes are accumulated in the charge accumulation node and a state where the holes are not accumulated in the charge accumulation node to thereby store data “1” and data “0”, respectively. An access transistor has impurity diffusion regions, a channel formation region, a gate oxide film, and a gate electrode. The impurity diffusion region is connected to a bit line.

Abstract: A pair of operator cells each having a series-coupled circuit of first and second transistors is used as a storage unit. To-be-retrieved data and retrieval data are respectively stored in the first and second transistors, and mutually complementary data items are stored in the operator cells of the storage unit. The operator cells supply currents according to the result of an AND operation between the stored data items to corresponding bit lines, and the read data from the storage unit corresponds to the result of an EXOR operation between the retrieval data and the to-be-retrieved data. The currents flowing in the corresponding bit lines are amplified with sense amplifier circuits to drive local match lines. In the individual sub-blocks of an operator cell array, data items having different pattern lengths can be stored. The potentials of the local match lines are selected according to the data pattern lengths, and match retrieval is performed for the data items having the different pattern lengths.

Abstract: The present invention aims at providing a semiconductor memory device that can be manufactured by a MOS process and can realize a stable operation. A storage transistor has impurity diffusion regions, a channel formation region, a charge accumulation node, a gate oxide film, and a gate electrode. The gate electrode is connected to a gate line and the impurity diffusion region is connected to a source line. The storage transistor creates a state where holes are accumulated in the charge accumulation node and a state where the holes are not accumulated in the charge accumulation node to thereby store data “1” and data “0”, respectively. An access transistor has impurity diffusion regions, a channel formation region, a gate oxide film, and a gate electrode. The impurity diffusion region is connected to a bit line.