Patents by Inventor Kazutami Arimoto
Kazutami Arimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7139208Abstract: In a data holding mode, data storage in a one bit/one cell scheme in a normal operating mode are rearranged into data storage in a twin-cell mode in which data are stored in a one bit/two cell scheme. In the twin-cell mode, two sub word lines are simultaneously driven into a selected state, and storage data of memory cells are read out on both of bit lines in a pair, to perform a sense operation. Thus, the read-out voltage can be increased to improve the data retention characteristics for lengthening a refresh interval, resulting in a reduced power consumption in the data holding mode.Type: GrantFiled: June 24, 2005Date of Patent: November 21, 2006Assignee: Renesas Technology Corp.Inventors: Kazutami Arimoto, Hiroki Shimano, Takeshi Fujino, Takeshi Hashizume
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Patent number: 7102954Abstract: In a memory circuit, a transistor formed in the same process as that of a logic transistor is used for peripheral circuitry except for a region to be supplied with high voltage. Thus, the manufacturing process can be simplified and a logic-merged memory operating at a high speed is provided.Type: GrantFiled: November 17, 2003Date of Patent: September 5, 2006Assignee: Renesas Technology Corp.Inventors: Hideyuki Noda, Kazutami Arimoto, Katsumi Dosaka, Takeshi Fujino
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Publication number: 20060193164Abstract: Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus. a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.Type: ApplicationFiled: April 5, 2006Publication date: August 31, 2006Applicant: RENESAS TECHNOLOGY CORP.Inventors: Kazutami Arimoto, Hiroki Shimano
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Publication number: 20060143428Abstract: An orthogonal memory for transforming arrangements of system bus data and processing data is placed between a system bus interface and a memory cell mat storing the processing data. The orthogonal memory includes two-port memory cells, and changes data train transferred in a bit parallel and word serial fashion into a data train of word parallel and bit serial data. Data transfer efficiency in a signal processing device performing parallel operational processing can be increased without impairing parallelism of the processing.Type: ApplicationFiled: November 21, 2005Publication date: June 29, 2006Inventors: Hideyuki Noda, Kazutami Arimoto, Katsumi Dosaka, Kazunori Saito
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Patent number: 7046543Abstract: Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus, a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.Type: GrantFiled: August 23, 2004Date of Patent: May 16, 2006Assignee: Renesas Technology Corp.Inventors: Kazutami Arimoto, Hiroki Shimano
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Publication number: 20060013030Abstract: In a data holding mode, data storage in a one bit/one cell scheme in a normal operating mode are rearranged into data storage in a twin-cell mode in which data are stored in a one bit/two cell scheme. In the twin-cell mode, two sub word lines are simultaneously driven into a selected state, and storage data of memory cells are read out on both of bit lines in a pair, to perform a sense operation. Thus, the read-out voltage can be increased to improve the data retention characteristics for lengthening a refresh interval, resulting in a reduced power consumption in the data holding mode.Type: ApplicationFiled: June 24, 2005Publication date: January 19, 2006Applicant: Renesas Technology Corp.Inventors: Kazutami Arimoto, Hiroki Shimano, Takeshi Fujino, Takeshi Hashizume
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Patent number: 6980454Abstract: A memory cell unit includes a first storage element and a second storage element for storing complementary data with each other. In a selected state, the first and second storage elements are connected to complementary bit lines, respectively at a time. In a standby state, the bit lines are precharged to a voltage (Vccs or GND) corresponding to the data stored in the memory cell unit. Refresh-free, low-current-consumption semiconductor memory device operating stably even under a low power supply voltage can be implemented.Type: GrantFiled: September 27, 2004Date of Patent: December 27, 2005Assignee: Renesas Technology Corp.Inventors: Takeshi Fujino, Kazutami Arimoto, Hiroki Shimano
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Patent number: 6925022Abstract: In a data holding mode, data storage in a one bit/one cell scheme in a normal operating mode are rearranged into data storage in a twin-cell mode in which data are stored in a one bit/two cell scheme. In the twin-cell mode, two sub word lines are simultaneously driven into a selected state, and storage data of memory cells are read out on both of bit lines in a pair, to perform a sense operation. Thus, the read-out voltage can be increased to improve the data retention characteristics for lengthening a refresh interval, resulting in a reduced power consumption in the data holding mode.Type: GrantFiled: August 28, 2002Date of Patent: August 2, 2005Assignee: Renesas Technology Corp.Inventors: Kazutami Arimoto, Hiroki Shimano, Takeshi Fujino, Takeshi Hashizume
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Patent number: 6909658Abstract: A self refresh timer is set constantly to an operation state to render a refresh request signal FAY active periodically. When contention occurs between the refresh request signal FAY and an externally applied read or write command, a row selection related circuit/command generation related circuit controls a row related control signal so that a refresh operation is carried out after, for example, the read or write operation ends. A submemory array SMA is divided more small than that of the conventional case, and the refresh cycle ends in a shorter period of time. Therefore, a read operation and a refresh operation can be completed within a read cycle time. A DRAM core that can be employed with control as simple as that of an SRAM can be realized.Type: GrantFiled: May 11, 2004Date of Patent: June 21, 2005Assignee: Renesas Technology Corp.Inventors: Kazutami Arimoto, Hiroki Shimano
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Patent number: 6898137Abstract: In a Vss precharge scheme, dummy cells including a bit line contact, a storage node contact and a third contact connected to a Vccs power supply line are arranged in complementary bit lines. In a waiting state, H level data is written in each dummy cell from the Vccs power supply line. Before row activation is started and a normal word line is selected, a dummy word line is driven to a selected state, and the H level data is read from each dummy cell. Therefore, charge in equal amounts is injected to the complementary bit lines, and a shift from a Vss level to the same potential occurs. A sense amplifier uses the potential as a reference voltage to amplify and detect a potential difference between bit lines.Type: GrantFiled: April 1, 2003Date of Patent: May 24, 2005Assignee: Renesas Technology Corp.Inventors: Kazutami Arimoto, Hiroki Shimano
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Publication number: 20050041514Abstract: A memory cell unit includes a first storage element and a second storage element for storing complementary data with each other. In a selected state, the first and second storage elements are connected to complementary bit lines, respectively at a time. In a standby state, the bit lines are precharged to a voltage (Vccs or GND) corresponding to the data stored in the memory cell unit. Refresh-free, low-current-consumption semiconductor memory device operating stably even under a low power supply voltage can be implemented.Type: ApplicationFiled: September 27, 2004Publication date: February 24, 2005Applicant: Renesas Technology Corp.Inventors: Takeshi Fujino, Kazutami Arimoto, Hiroki Shimano
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Patent number: 6859403Abstract: Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss?, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss?.Type: GrantFiled: April 2, 2004Date of Patent: February 22, 2005Assignee: Renesas Technology Corp.Inventors: Hideto Hidaka, Mikio Asakura, Kazuyasu Fujishima, Tsukasa Ooishi, Kazutami Arimoto, Shigeki Tomishima, Masaki Tsukude
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Publication number: 20050018471Abstract: Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus, a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.Type: ApplicationFiled: August 23, 2004Publication date: January 27, 2005Applicant: RENESAS TECHNOLOGY CORP.Inventors: Kazutami Arimoto, Hiroki Shimano
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Publication number: 20040208076Abstract: A self refresh timer is set constantly to an operation state to render a refresh request signal FAY active periodically. When contention occurs between the refresh request signal FAY and an externally applied read or write command, a row selection related circuit/command generation related circuit controls a row related control signal so that a refresh operation is carried out after, for example, the read or write operation ends. A submemory array SMA is divided more small than that of the conventional case, and the refresh cycle ends in a shorter period of time. Therefore, a read operation and a refresh operation can be completed within a read cycle time. A DRAM core that can be employed with control as simple as that of an SRAM can be realized.Type: ApplicationFiled: May 11, 2004Publication date: October 21, 2004Applicant: Renesas Technology Corp.Inventors: Kazutami Arimoto, Hiroki Shimano
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Patent number: 6804164Abstract: A memory cell unit includes a first storage element and a second storage element for storing complementary data with each other. In a selected state, the first and second storage elements are connected to complementary bit lines, respectively at a time. In a standby state, the bit lines are precharged to a voltage (Vccs or GND) corresponding to the data stored in the memory cell unit. Refresh-free, low-current-consumption semiconductor memory device operating stably even under a low power supply voltage can be implemented.Type: GrantFiled: May 14, 2003Date of Patent: October 12, 2004Assignee: Renesas Technology Corp.Inventors: Takeshi Fujino, Kazutami Arimoto, Hiroki Shimano
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Publication number: 20040184332Abstract: Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss′, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss′.Type: ApplicationFiled: April 2, 2004Publication date: September 23, 2004Applicant: RENESAS TECHNOLOGY CORP.Inventors: Hideto Hidaka, Mikio Asakura, Kazuyasu Fujishima, Tsukasa Ooishi, Kazutami Arimoto, Shigeki Tomishima, Masaki Tsukude
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Patent number: 6785157Abstract: Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus, a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.Type: GrantFiled: April 10, 2002Date of Patent: August 31, 2004Assignee: Renesas Technology Corp.Inventors: Kazutami Arimoto, Hiroki Shimano
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Patent number: 6781915Abstract: Memory cells are arranged such that one-bit data is stored by two-bit memory cells. The cell plate electrode of the memory cell capacitor and the gate electrode of the memory cell transistor are formed in the same manufacturing step. The amplitude of an isolation control signal applied to a bit line isolation gate connecting the bit line and the sense amplifier is restricted, and the word line is driven according to a negative voltage non-boosted word line scheme. A well region where a memory block is formed and a well region where the isolation gate is formed are separately provided, and separate bias voltages are applied thereto. Thus, a DRAM (dynamic random access memory)-based logic merged memory is implemented without degrading dielectric breakdown characteristics of the gate insulating film.Type: GrantFiled: October 22, 2002Date of Patent: August 24, 2004Assignee: Renesas Technology Corp.Inventors: Kazutami Arimoto, Hiroki Shimano
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Publication number: 20040136230Abstract: In a memory circuit, a transistor formed in the same process as that of a logic transistor is used for peripheral circuitry except for a region to be supplied with high voltage. Thus, the manufacturing process can be simplified and a logic-merged memory operating at a high speed is provided.Type: ApplicationFiled: November 17, 2003Publication date: July 15, 2004Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Hideyuki Noda, Kazutami Arimoto, Katsumi Dosaka, Takeshi Fujino
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Patent number: 6744684Abstract: A self refresh timer is set constantly to an operation state to render a refresh request signal FAY active periodically. When contention occurs between the refresh request signal FAY and an externally applied read or write command, a row selection related circuit/command generation related circuit controls a row related control signal so that a refresh operation is carried out after, for example, the read or write operation ends. A submemory array SMA is divided more small than that of the conventional case, and the refresh cycle ends in a shorter period of time. Therefore, a read operation and a refresh operation can be completed within a read cycle time. A DRAM core that can be employed with control as simple as that of an SRAM can be realized.Type: GrantFiled: February 7, 2001Date of Patent: June 1, 2004Assignee: Reneses Technology Corp.Inventors: Kazutami Arimoto, Hiroki Shimano