Patents by Inventor Kazuya Hanaoka
Kazuya Hanaoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20140127868Abstract: A miniaturized transistor is provided with high yield. Further, a semiconductor device which has high on-state characteristics and which is capable of high-speed response and high-speed operation is provided. In the semiconductor device, an oxide semiconductor layer, a gate insulating layer, a gate electrode layer, an insulating layer, a conductive film, and an interlayer insulating layer are stacked in this order. A source electrode layer and a drain electrode layer are formed in a self-aligned manner by cutting the conductive film so that the conductive film over the gate electrode layer and the conductive layer is removed and the conductive film is divided. An electrode layer which is in contact with the oxide semiconductor layer and overlaps with a region in contact with the source electrode layer and the drain electrode layer is provided.Type: ApplicationFiled: January 9, 2014Publication date: May 8, 2014Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toshihiko SAITO, Atsuo ISOBE, Kazuya HANAOKA, Junichi KOEZUKA, Shinya SASAGAWA, Motomu KURATA, Akihiro ISHIZUKA
-
Patent number: 8698697Abstract: In a semiconductor device in which a copper plating layer is used for a conductor of an antenna and in which an integrated circuit and the antenna are formed over the same substrate, an object is to prevent an adverse effect on electrical characteristics of a circuit element due to diffusion of copper, as well as to provide a copper plating layer with favorable adhesiveness. Another object is to prevent a defect in the semiconductor device that stems from poor connection between the antenna and the integrated circuit, in the semiconductor device in which the integrated circuit and the antenna are formed over the same substrate. In the semiconductor device, a copper plating layer is used for the antenna, an alloy of Ag, Pd, and Cu is used for a seed layer thereof, and TiN or Ti is used for a barrier layer.Type: GrantFiled: June 9, 2008Date of Patent: April 15, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Teruyuki Fujii, Kazuya Hanaoka
-
Patent number: 8664118Abstract: An object is to provide a semiconductor device having excellent characteristics, in which a channel layer includes an oxide semiconductor with high crystallinity. In addition, a semiconductor device including a base film with improved planarity is provided. CMP treatment is performed on the base film of the transistor and plasma treatment is performed thereon after the CMP treatment, whereby the base film can have a center line average roughness Ra75 of less than 0.1 nm. The oxide semiconductor layer with high crystallinity is formed over the base film having planarity, which is obtained by the combination of the plasma treatment and the CMP treatment, thereby improving the characteristics of the semiconductor device.Type: GrantFiled: July 2, 2012Date of Patent: March 4, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Akihiro Ishizuka, Kazuya Hanaoka, Shinya Sasagawa, Sho Nagamatsu
-
Patent number: 8637864Abstract: A miniaturized transistor is provided with high yield. Further, a semiconductor device which has high on-state characteristics and which is capable of high-speed response and high-speed operation is provided. In the semiconductor device, an oxide semiconductor layer, a gate insulating layer, a gate electrode layer, an insulating layer, a conductive film, and an interlayer insulating layer are stacked in this order. A source electrode layer and a drain electrode layer are formed in a self-aligned manner by cutting the conductive film so that the conductive film over the gate electrode layer and the conductive layer is removed and the conductive film is divided. An electrode layer which is in contact with the oxide semiconductor layer and overlaps with a region in contact with the source electrode layer and the drain electrode layer is provided.Type: GrantFiled: October 1, 2012Date of Patent: January 28, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toshihiko Saito, Atsuo Isobe, Kazuya Hanaoka, Junichi Koezuka, Shinya Sasagawa, Motomu Kurata, Akihiro Ishizuka
-
Publication number: 20130320332Abstract: A transistor including an oxide semiconductor film, which has stable electric characteristics is provided. A transistor including an oxide semiconductor film, which has excellent on-state characteristics is also provided. A semiconductor device in which an oxide semiconductor film having low resistance is formed and the resistance of a channel region of the oxide semiconductor film is increased. Note that an oxide semiconductor film is subjected to a process for reducing the resistance to have low resistance. The process for reducing the resistance of the oxide semiconductor film may be a laser process or heat treatment at a temperature higher than or equal to 450° C. and lower than or equal to 740° C., for example. A process for increasing the resistance of the channel region of the oxide semiconductor film having low resistance may be performed by plasma oxidation or implantation of oxygen ions, for example.Type: ApplicationFiled: May 20, 2013Publication date: December 5, 2013Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Suguru HONDO, Akihisa SHIMOMURA, Masaki KOYAMA, Motomu KURATA, Kazuya HANAOKA, Sho NAGAMATSU, Kosei NEI, Toru HASEGAWA
-
Publication number: 20130267068Abstract: In a processing method of a stacked-layer film in which a metal film is provided on an oxide insulating film, plasma containing an oxygen ion is generated by applying high-frequency power with power density greater than or equal to 0.59 W/cm2 and less than or equal to 1.18 W/cm2 to the stacked-layer film side under an atmosphere containing oxygen in which pressure is greater than or equal to 5 Pa and less than or equal to 15 Pa, the metal film is oxidized by the oxygen ion, and an oxide insulating film containing excess oxygen is formed by supplying oxygen to the oxide insulating film.Type: ApplicationFiled: April 1, 2013Publication date: October 10, 2013Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kazuya Hanaoka, Shinya Sasagawa
-
Patent number: 8530973Abstract: It is an object to form a conductive region in an insulating film without forming contact holes in the insulating film. A method is provided, in which an insulating film is formed over a first electrode over a substrate, a first region having many defects is formed at a first depth in the insulating film by adding first ions into the insulating film at a first accelerating voltage; a second region having many defects is formed at a second depth which is different from the first depth in the insulating film by adding second ions into the insulating film at a second accelerating voltage, a conductive material containing a metal element is formed over the first and second regions; and a conductive region which electrically connects the first electrode and the conductive material is formed in the insulating film by diffusing the metal element into the first and second regions.Type: GrantFiled: July 12, 2012Date of Patent: September 10, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kazuya Hanaoka, Miki Suzuki
-
Patent number: 8486772Abstract: The method of one embodiment of the present invention includes: a first step of irradiating a bond substrate with ions to form an embrittlement region in the bond substrate; a second step of bonding the bond substrate to a base substrate with an insulating layer therebetween; a third step of splitting the bond substrate at the embrittlement region to form a semiconductor layer over the base substrate with the insulating layer therebetween; and a fourth step of subjecting the bond substrate split at the embrittlement region to a first heat treatment in an argon atmosphere and then a second heat treatment in an atmosphere of a mixture of oxygen and nitrogen to form a reprocessed bond substrate. The reprocessed bond substrate is used again as a bond substrate in the first step.Type: GrantFiled: April 24, 2012Date of Patent: July 16, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kazuya Hanaoka, Hideki Tsuya, Masaharu Nagai
-
Patent number: 8415228Abstract: To provide a manufacturing method of a semiconductor device in which, even when the semiconductor device is formed over an SOI substrate which uses a glass substrate, an insulating film and a semiconductor film over the glass substrate are not peeled by stress applied by a conductive film in formation of the conductive film for forming a gate electrode.Type: GrantFiled: September 9, 2009Date of Patent: April 9, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kazuya Hanaoka, Takashi Shingu, Taichi Endo
-
Publication number: 20130075732Abstract: A miniaturized transistor having high electric characteristics is provided with high yield. In a semiconductor device including the transistor, high performance, high reliability, and high productivity are achieved. In a semiconductor device including a transistor in which an oxide semiconductor film, a gate insulating film, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, source and drain electrode layers are provided in contact with the oxide semiconductor film and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive film and an interlayer insulating film are stacked to cover the oxide semiconductor film, the sidewall insulating layers, and the gate electrode layer, and the interlayer insulating film and the conductive film over the gate electrode layer are removed by a chemical mechanical polishing method, so that the source and drain electrode layers are formed.Type: ApplicationFiled: September 6, 2012Publication date: March 28, 2013Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Toshihiko SAITO, Atsuo ISOBE, Kazuya HANAOKA, Junichi KOEZUKA, Shinya SASAGAWA, Motomu KURATA, Akihiro ISHIZUKA
-
Publication number: 20130075733Abstract: A minute transistor and the method of manufacturing the minute transistor. A source electrode layer and a drain electrode layer are each formed in a corresponding opening formed in an insulating layer covering a semiconductor layer. The opening of the source electrode layer and the opening of the drain electrode layer are formed separately in two distinct steps. The source electrode layer and the drain electrode layer are formed by depositing a conductive layer over the insulating layer and in the openings, and subsequently removing the part located over the insulating layer by polishing. This manufacturing method allows for the source electrode later and the drain electrode layer to be formed close to each other and close to a channel forming region of the semiconductor layer. Such a structure leads to a transistor having high electrical characteristics and a high manufacturing yield even in the case of a minute structure.Type: ApplicationFiled: September 11, 2012Publication date: March 28, 2013Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Toshihiko SAITO, Atsuo ISOBE, Kazuya HANAOKA, Sho NAGAMATSU
-
Patent number: 8404563Abstract: The embrittlement layer and the semiconductor layer remaining on the periphery of the semiconductor substrate after separation are selectively removed using a mixed solution containing a substance functioning as an oxidizer for oxidizing a semiconductor, a substance dissolving an oxide of a semiconductor, and a substance functioning as a decelerator of oxidization of a semiconductor and dissolution of an oxide of a semiconductor. Note that the semiconductor film is separated from the semiconductor substrate along an embrittlement layer that is formed in the semiconductor substrate by implantation of an H+ ion generated from a hydrogen gas with use of an ion implantation apparatus.Type: GrantFiled: June 22, 2010Date of Patent: March 26, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Kazuya Hanaoka
-
Patent number: 8384601Abstract: An object of the present invention is to prevent electrical characteristics of circuit elements from being adversely affected by copper diffusion in a semiconductor device having an integrated circuit and an antenna formed over one substrate, which uses copper plating for the antenna. Another object is to prevent a defect of a semiconductor device due to poor connection between an antenna and an integrated circuit in a semiconductor device having the integrated circuit and the antenna formed over one substrate. In a semiconductor device having an integrated circuit 100 and an antenna 101 formed over one substrate 102, when a copper plating layer 108 is used for a conductor of the antenna 101, it is possible to decrease an adverse effect on electrical characteristics of circuit elements due to copper diffusion because a base layer 107 of the antenna 101 uses a nitride film of a predetermined metal.Type: GrantFiled: January 31, 2012Date of Patent: February 26, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kazuya Hanaoka, Hideto Ohnuma, Teruyuki Fujii
-
Patent number: 8367517Abstract: An insulating layer is formed over a surface of a semiconductor wafer to be the bond substrate and irradiation with accelerated ions is performed, so that an embrittlement region is formed inside the wafer. Next, this semiconductor wafer and a base substrate such as a glass substrate or a semiconductor wafer are attached to each other. Then, the semiconductor wafer is divided at the embrittlement region by heat treatment, whereby an SOI substrate is manufactured in which a semiconductor layer is provided over the base substrate with the insulating layer interposed therebetween. Before this SOI substrate is manufactured, heat treatment is performed on the semiconductor wafer at 1100° C. or higher under a non-oxidizing atmosphere such as an argon gas atmosphere or a mixed atmosphere of an oxygen gas and a nitrogen gas.Type: GrantFiled: January 21, 2011Date of Patent: February 5, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kazuya Hanaoka, Hideki Tsuya, Yoshihiro Komatsu
-
Publication number: 20130023108Abstract: An insulating layer is formed on a surface of a semiconductor wafer which is to be a bond substrate and an embrittlement region is formed in the semiconductor wafer by irradiation with accelerated ions. Then, a base substrate and the semiconductor wafer are attached to each other. After that, the semiconductor wafer is divided at the embrittlement region by performing heat treatment and an SOI substrate including a semiconductor layer over the base substrate with the insulating layer interposed therebetween is formed. Before the SOI substrate is formed, heat treatment is performed on the semiconductor wafer at a temperature of higher than or equal to 1100° C. under a non-oxidizing atmosphere in which the concentration of impurities is reduced. In this manner, the planarity of the film formed on the semiconductor wafer when heat treatment is performed can be improved.Type: ApplicationFiled: July 18, 2012Publication date: January 24, 2013Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Kazuya HANAOKA, Yujiro SAKURADA, Hideki TSUYA, Makoto FURUNO, Miku FUJITA
-
Patent number: 8354348Abstract: An object is to provide a method suitable for reprocessing a semiconductor substrate which is reused to manufacture an SOI substrate. A semiconductor substrate is reprocessed in the following manner: etching treatment is performed on a semiconductor substrate in which a projection including a damaged semiconductor region and an insulating layer exists in a peripheral portion, whereby the insulating layer is removed; and etching treatment is performed on the semiconductor substrate with the use of a mixed solution including a substance that oxidizes a semiconductor material included in the semiconductor substrate, a substance that dissolves the oxidized semiconductor material, and a substance that controls oxidation speed of the semiconductor material and dissolution speed of the oxidized semiconductor material, whereby the damaged semiconductor region is selectively removed with a non-damaged semiconductor region left.Type: GrantFiled: August 19, 2010Date of Patent: January 15, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kazuya Hanaoka, Keitaro Imai
-
Publication number: 20130009247Abstract: It is an object to form a conductive region in an insulating film without forming contact holes in the insulating film. A method is provided, in which an insulating film is formed over a first electrode over a substrate, a first region having many defects is formed at a first depth in the insulating film by adding first ions into the insulating film at a first accelerating voltage; a second region having many defects is formed at a second depth which is different from the first depth in the insulating film by adding second ions into the insulating film at a second accelerating voltage, a conductive material containing a metal element is formed over the first and second regions; and a conductive region which electrically connects the first electrode and the conductive material is formed in the insulating film by diffusing the metal element into the first and second regions.Type: ApplicationFiled: July 12, 2012Publication date: January 10, 2013Inventors: Kazuya Hanaoka, Miki Suzuki
-
Publication number: 20130011961Abstract: An object is to provide a semiconductor device having excellent characteristics, in which a channel layer includes an oxide semiconductor with high crystallinity. In addition, a semiconductor device including a base film with improved planarity is provided. CMP treatment is performed on the base film of the transistor and plasma treatment is performed thereon after the CMP treatment, whereby the base film can have a center line average roughness Ra75 of less than 0.1 nm. The oxide semiconductor layer with high crystallinity is formed over the base film having planarity, which is obtained by the combination of the plasma treatment and the CMP treatment, thereby improving the characteristics of the semiconductor device.Type: ApplicationFiled: July 2, 2012Publication date: January 10, 2013Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Akihiro ISHIZUKA, Kazuya HANAOKA, Shinya SASAGAWA, Sho NAGAMATSU
-
Publication number: 20120329242Abstract: A method suitable to reprocess a semiconductor substrate is provided. A semiconductor substrate in which a projection including a damaged semiconductor region and an insulating layer is provided in a peripheral portion of the semiconductor substrate is subjected to etching treatment for removing the insulating layer and to etching treatment for removing the damaged semiconductor region selectively with a non-damaged semiconductor region left using a mixed solution including nitric acid, a substance dissolving a semiconductor material included in the semiconductor substrate and oxidized by the nitric acid, a substance controlling a speed of oxidation of the semiconductor material and a speed of dissolution of the oxidized semiconductor material, and nitrous acid, in which the concentration of the nitrous acid is higher than or equal to 10 mg/l and lower than or equal to 1000 mg/l. Through these steps, the semiconductor substrate is reprocessed.Type: ApplicationFiled: June 14, 2012Publication date: December 27, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Kazuya HANAOKA, Shunsuke KIMURA
-
Patent number: 8288245Abstract: An object of an embodiment of the disclosed invention is to provide a method suitable for reprocessing a semiconductor substrate which is reused to manufacture an SOI substrate.Type: GrantFiled: September 30, 2010Date of Patent: October 16, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hideto Ohnuma, Kazuya Hanaoka