Patents by Inventor Kazuya Yamamoto
Kazuya Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090174484Abstract: An amplifying transistor for amplifying a radio frequency signal between an input terminal and an output terminal. The cathode of a first diode is connected to the input terminal and the anode of a second diode is connected to the output terminal. A matching and attenuating circuit is connected between the anode of the first diode and the cathode of the second diode. A matching and attenuating circuit reduces impedance mismatches on the input terminal side and the output terminal side, and attenuates the radio frequency signal. In an amplification mode, a bias circuit supplies a bias current to an amplifying transistor and a current mirror circuit turns off the first and second diodes. In an attenuation mode, the bias circuit supplies no bias current to the amplifying transistor and the current mirror circuit turns on the first and second diodes.Type: ApplicationFiled: June 3, 2008Publication date: July 9, 2009Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Kazuya Yamamoto, Miyo Miyashita
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Publication number: 20090124083Abstract: A method for using a film formation apparatus for a semiconductor process to form a thin film on a target substrate while supplying a film formation reactive gas from a first nozzle inside a reaction chamber includes performing a cleaning process to remove a by-product film deposited inside the reaction chamber and the first nozzle, in a state where the reaction chamber does not accommodate the target substrate. The cleaning process includes, in order, an etching step of supplying a cleaning reactive gas for etching the by-product film into the reaction chamber, and activating the cleaning reactive gas, thereby etching the by-product film, and an exhaust step of stopping supply of the cleaning reactive gas and exhausting gas from inside the reaction chamber. The etching step is arranged to use conditions that cause the cleaning reactive gas supplied in the reaction chamber to flow into the first nozzle.Type: ApplicationFiled: October 8, 2008Publication date: May 14, 2009Inventors: Nobutake Nodera, Jun Sato, Kazuya Yamamoto, Kazuhide Hasebe
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Publication number: 20090114156Abstract: A film formation apparatus for a semiconductor process includes a support member having a plurality of support levels configured to support target substrates inside a reaction chamber; a film formation gas supply system configured to supply a film formation gas into the reaction chamber and including a gas distribution nozzle; a cleaning gas supply system configured to supply a cleaning gas for etching a by-product film deposited inside the reaction chamber; and an exhaust system configured to exhaust gas from inside the reaction chamber. The cleaning gas supply system includes a gas nozzle disposed near a bottom of the reaction chamber and having a gas supply port at its top directed upward, and the gas supply port is located below the lowermost one of the support levels of the support member.Type: ApplicationFiled: October 7, 2008Publication date: May 7, 2009Inventors: Nobutake Nodera, Jun Sato, Kazuya Yamamoto, Kazuhide Hasebe
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Patent number: 7522001Abstract: An emitter follower circuit applies to an input terminal of a second amplifying device a voltage according to a reference voltage applied to a reference terminal. First and second resistors are connected in series between the reference terminal and an input terminal of a first amplifying device. The collector of a first transistor is connected to the reference terminal and a control voltage is applied to the base of the first transistor. A third resistor is connected between the emitter of the first transistor and a grounding point. A current mirror circuit draws a current proportional to a current input from the collector of the first transistor from a connection point of the first and second resistors.Type: GrantFiled: November 29, 2007Date of Patent: April 21, 2009Assignee: Mitsubishi Electric CorporationInventors: Kazuya Yamamoto, Miyo Miyashita
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Publication number: 20090066015Abstract: Guide ribs have curved inversion/transfer surfaces from an inversion start point corresponding to a first transport surface to an inversion end point corresponding to a second transport surface.Type: ApplicationFiled: August 6, 2008Publication date: March 12, 2009Inventors: Yoshihide Sugiyama, Nobuki Tanimoto, Kazuya Yamamoto, Katsunori Takahashi
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Publication number: 20090051104Abstract: There is provided a sheet inverting and conveying mechanism for conveying a sheet in a first direction, inverting obverse and reverse sides of the sheet, and then conveying the inverted sheet in a second direction. The mechanism includes: a first conveyance section for receiving, at its conveyance face, one side of the sheet, and for conveying the sheet in the first direction (the direction of an arrow S); a sheet inverting section for receiving, at its bent inner peripheral face, one side of the sheet, and for inverting the sheet while bending the sheet along the bent inner peripheral face; and a second conveyance section for receiving, at its conveyance face, one side of the inverted sheet, and for conveying the sheet in the second direction (the direction of an arrow T), wherein the first conveyance section and the second conveyance section are formed so that the sheet is conveyed while being attracted to the conveyance faces.Type: ApplicationFiled: March 5, 2007Publication date: February 26, 2009Applicant: Duplo Seiko CorporationInventors: Yoshihide Sugiyama, Kazuya Yamamoto
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Publication number: 20090051437Abstract: An emitter follower circuit applies to an input terminal of a second amplifying device a voltage according to a reference voltage applied to a reference terminals. First and second resistors are connected in series between the reference terminal and an input terminal of a first amplifying device. The collector of a first transistor is connected to the reference terminal, and a control voltage is applied to the base of the first transistor. A third resistor is connected between the emitter of the first transistor and a grounding point. A current mirror circuit draws a current proportional to a current input from the collector of the first transistor from a connection point of the first and second resistors.Type: ApplicationFiled: November 29, 2007Publication date: February 26, 2009Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Kazuya Yamamoto, Miyo Miyashita
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Publication number: 20090034079Abstract: This invention provides a mold with which a two-dimensional subwavelength grating can be produced with a higher percentage transfer by injection molding and a two-dimensional subwavelength grating having a high aspect ratio produced with such a mold. The mold for a fine grating according to the present invention has protrusion parts (107) arranged at an interval on the bottom face (103) of a cavity, wherein the interval is a distance between centers of the protrusion parts and a period of the fine grating smaller than wavelengths of visible lights. In one embodiment, a cross-section of the protrusion parts, parallel to the bottom face of the cavity decreases with height along the protrusion parts and a decreasing rate of the cross-section increases with height along the protrusions.Type: ApplicationFiled: May 22, 2006Publication date: February 5, 2009Applicant: Nalux Co., Ltd.Inventors: Kazuya Yamamoto, Makoto Okada
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Publication number: 20090027130Abstract: A power amplifier according to the present invention is operated by switching a main power amplifier and a subsidiary power amplifier. The idle current of the subsidiary power amplifier is smaller than the idle current of the main power amplifier. Each of the main power amplifier and the subsidiary power amplifier has a former amplification element for amplifying RF signals, a latter amplification element for amplifying output signals from the former amplification element, a former bias circuit for driving the former amplification elements, and a latter bias circuit for driving the latter amplification elements, respectively. The interval between the latter amplification element of the main power amplifier and the latter amplification element of the subsidiary power amplifier is not more than 100 ?m. The interval between the latter amplification element of the main power amplifier and the latter bias circuit of the subsidiary power amplifier is not less than 200 ?m.Type: ApplicationFiled: November 30, 2007Publication date: January 29, 2009Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Kazuya Yamamoto, Satoshi Suzuki, Tomoyuki Asada, Takayuki Matsuzuka, Teruyuki Shimura
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Patent number: 7474169Abstract: An attenuator includes a first diode, a first control voltage terminal, a second diode, a first resistance, a second resistance, a third diode, a fourth diode, a fifth capacitance, a second control voltage terminal, a third control voltage terminal, a fourth control voltage terminal, and a linearizer provided between an input terminal and the anode of the first diode. The linearizer linearizes a signal input to the input terminal only when low level voltages are applied to the first and fourth control voltage terminals at the same time that high level voltages are applied to the second and third control voltage terminals.Type: GrantFiled: October 27, 2006Date of Patent: January 6, 2009Assignee: Mitsubishi Electric CorporationInventors: Kazuya Yamamoto, Miyo Miyashita
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Patent number: 7474170Abstract: A linearizer includes fifth diodes, a third resistor, sixth diodes, and a first npn heterojunction bipolar transistor. When a low-level voltage is applied to first and fourth control voltage terminals and a high-level voltage is applied to second and third control voltage terminals, a low-level voltage is applied to a fifth control voltage terminal, and when a high-level voltage is applied to the first and fourth control voltage terminals and a low-level voltage is applied to the second and third control voltage terminals, a high-level voltage is applied to the fifth control voltage terminal.Type: GrantFiled: February 26, 2007Date of Patent: January 6, 2009Assignee: Mitsubishi Electric CorporationInventors: Kazuya Yamamoto, Miyo Miyashita
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Publication number: 20080238562Abstract: A voltage-controlled oscillator has an oscillation frequency controlled through a voltage applied across ends of a variable-capacitance element. The voltage-controlled oscillator has a frequency control bias circuit which applies to a first end of the variable-capacitance element a voltage for frequency control according to a control voltage, a first current source which generates a first current according to the control voltage, a second current source which generates a second current according to temperature, independent of the control voltage, a converting resistor which converts a current, obtained by adding together the first and second currents, into a voltage, and a temperature compensation bias circuit which applies to the second end of the variable-capacitance element a voltage for temperature compensation according to the voltage produced by the converting resistor.Type: ApplicationFiled: November 7, 2007Publication date: October 2, 2008Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Takayuki Matsuzuka, Kazuya Yamamoto
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Publication number: 20080212846Abstract: Tools and techniques for biometric authentication obtain a biologic information input such as a fingerprint image, which is to be accepted or rejected as being input from an authentic user. Calculated matching scores show respective degrees of similarity between the biologic information input and several templates. The templates include a fixed registration biologic information template, as well as non-fixed learning biologic information templates which are subject to replacement.Type: ApplicationFiled: December 26, 2007Publication date: September 4, 2008Inventors: Kazuya Yamamoto, Shota Ichikawa, Koji Hamaguchi
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Patent number: 7417507Abstract: A combined bias circuit in which a voltage drive bias circuit and a current drive bias circuit are provided in parallel with each other has a configuration in which a linearizer including a first resistor is connected between an amplifying transistor and a second resistor. This configuration ensures that even when a low voltage of 2.4 to 2.5 V is supplied as an external reference voltage, the amplifying operation can be performed while generally constantly maintaining an idling current in a temperature range from a low temperature to a high temperature, and that degradation in distortion characteristics during low-temperature operation can be limited.Type: GrantFiled: November 3, 2006Date of Patent: August 26, 2008Assignee: Mitsubishi Electric CorporationInventors: Kazuya Yamamoto, Tomoyuki Asada, Hiroyuki Otsuka, Kosei Maemura
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Patent number: 7408412Abstract: There are provided a power amplifying transistor, a bias circuit which supplies a bias current to the base of the power amplifying transistor, a current mirror circuit which detects a peak value of the collector voltage of the power amplifying transistor, and a control circuit which, when the peak value of the collector voltage becomes higher than a voltage set in advance, controls the bias circuit to increase the bias current.Type: GrantFiled: September 7, 2006Date of Patent: August 5, 2008Assignee: Mitsubishi Electric CorporationInventors: Kazuya Yamamoto, Tomoyuki Asada
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Publication number: 20080174356Abstract: A wave detector circuit includes: a first transistor having its base and collector connected together, the first transistor receiving an AC signal and a reference voltage at its base and collector; a second transistor having its base connected to the base of the first transistor through a resistance, the second transistor outputting a detected voltage at its collector; and a diode-connected temperature compensation transistor connected between ground potential and the base and the collector of the first transistor.Type: ApplicationFiled: May 15, 2007Publication date: July 24, 2008Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Kazuya YAMAMOTO, Miyo MIYASHITA, Takayuki MATSUZUKA
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Patent number: 7400202Abstract: A bias circuit includes a resistor in parallel with a voltage-drive bias circuit including a GaAs-HBT transistor. This configuration ensures that a current can be supplied from a reference voltage input terminal to the base terminal of a first transistor via the resistor in an idling state in which a voltage applied to the base terminal is lower than a voltage at which a second transistor operates, thereby enabling a desired amplifying operation while maintaining the idling current generally constant in a temperature range, even when the reference voltage is reduced to a value lower than twice the barrier voltage of the GaAs HBT.Type: GrantFiled: October 25, 2006Date of Patent: July 15, 2008Assignee: Mitsubishi Electric CorporationInventors: Kazuya Yamamoto, Kousei Maemura
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Publication number: 20080088392Abstract: A linearizer includes fifth diodes, a third resistor, sixth diodes, and a first n-channel MOS transistor. When a low-level voltage is applied to first and fourth control voltage terminals and a high-level voltage is applied to second and third control voltage terminals, a low-level voltage is applied to a fifth control voltage terminal, and when a high-level voltage is applied to the first and fourth control voltage terminals and a low-level voltage is applied to the second and third control voltage terminals, a high-level voltage is applied to the fifth control voltage terminal.Type: ApplicationFiled: February 26, 2007Publication date: April 17, 2008Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Kazuya YAMAMOTO, Miyo MIYASHITA
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Publication number: 20080003362Abstract: A method for using a film formation apparatus includes performing film formation of a product film selected from the group consisting of a silicon nitride film and a silicon oxynitride film on a target substrate within a reaction chamber of the film formation apparatus; and unloading the target substrate from the reaction chamber. Thereafter, the method includes first heating an inner surface of the reaction chamber at a post process temperature while supplying a post process gas for nitridation into the reaction chamber, thereby performing nitridation of a by-product film deposited on the inner surface of the reaction chamber; then rapidly cooling the inner surface of the reaction chamber, thereby cracking the by-product film by a thermal stress; and then forcibly exhausting gas from inside the reaction chamber to carry the by-product film, thus peeled off from the inner surface.Type: ApplicationFiled: June 27, 2007Publication date: January 3, 2008Inventors: Nobutake Nodera, Kazuhide Hasebe, Kazuya Yamamoto
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Publication number: 20070273447Abstract: A combined bias circuit in which a voltage drive bias circuit and a current drive bias circuit are provided in parallel with each other has a configuration in which a linearizer including a first resistor is connected between an amplifying transistor and a second resistor. This configuration ensures that even when a low voltage of 2.4 to 2.5 V is supplied as an external reference voltage, the amplifying operation can be performed while generally constantly maintaining an idling current in a temperature range from a low temperature to a high temperature, and that degradation in distortion characteristics during low-temperature operation can be limited.Type: ApplicationFiled: November 3, 2006Publication date: November 29, 2007Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Kazuya YAMAMOTO, Tomoyuki ASADA, Hiroyuki OTSUKA, Kosei MAEMURA