Abstract: A combined bias circuit in which a voltage drive bias circuit and a current drive bias circuit are provided in parallel with each other has a configuration in which a linearizer including a first resistor is connected between an amplifying transistor and a second resistor. This configuration ensures that even when a low voltage of 2.4 to 2.5 V is supplied as an external reference voltage, the amplifying operation can be performed while generally constantly maintaining an idling current in a temperature range from a low temperature to a high temperature, and that degradation in distortion characteristics during low-temperature operation can be limited.

Abstract: An attenuator includes a first diode, a first control voltage terminal, a second diode, a first resistance, a second resistance, a third diode, a fourth diode, a fifth capacitance, a second control voltage terminal, a third control voltage terminal, a fourth control voltage terminal, and a linearizer provided between an input terminal and the anode of the first diode. The linearizer linearizes a signal input to the input terminal only when low level voltages are applied to the first and fourth control voltage terminals at the same time that high level voltages are applied to the second and third control voltage terminals.

Abstract: After detection of contact between respective solder bumps of an electronic component, sucked and held by a suction nozzle of a head tool, and respective solder portions of a circuit board, the solder bumps and the solder portions are melted by heating. Releasing of the electronic component from suction and holding by the suction nozzle of the head tool is performed, not at a time during solder melting, but at a time after the solder is melted, cooled and solidified. Thus, an electronic component mounting method and apparatus capable of mounting high-end electronic components having narrow-pitched bumps are provided.

Abstract: A multiplier core outputs a single-phase signal containing a frequency component having a frequency which is an even multiple of the frequency of an input signal. A differential amplifier includes first and second nMOS transistors having respective source terminals connected to each other. The output signal from the multiplier core is inputted to the gate terminal of the first nMOS transistor, and the gate terminal of the second nMOS transistor is AC grounded. The differential amplifier differentially amplifies the signals inputted to the gate terminals of the first and second nMOS transistors to output a potential at the drain terminals of the first and second nMOS transistors as a differential signal. The output terminal of the multiplier core is connected through a series LC circuit to the source terminals of the first and second nMOS transistors.

Abstract: A bias circuit includes a resistor in parallel with a voltage-drive bias circuit including GaAs-HBT transistor. This configuration ensures that a current can be supplied from a reference voltage input terminal to the base terminal of a first transistor via the resistor in an idling state in which a voltage applied to the base terminal is lower than a voltage at which a second transistor operates, thereby enabling a desired amplifying operation while maintaining the idling current generally constant in a temperature range, even when the reference voltage is reduced to a value lower than twice the barrier voltage of the GaAs HBT.

Abstract: In a driver circuit including transistors each having an emitter follower configuration and a pair of differential transistors with emitter outputs of the transistors of the emitter follower configuration as inputs, end terminals of the pair of differential transistors are connected to individual bonding pads, and the respective bonding pads and voltage sources are individually connected by wires that function as inductors. Thereby, even in the case where the lengths of the wires of output terminals change according to packaging, outputs can be matched by determining the wire lengths of the wires suitably.

Abstract: There are provided a power amplifying transistor, a bias circuit which supplies a bias current to the base of the power amplifying transistor, a current mirror circuit which detects a peak value of the collector voltage of the power amplifying transistor, and a control circuit which, when the peak value of the collector voltage becomes higher than a voltage set in advance, controls the bias circuit to increase the bias current.

Abstract: Diodes and are connected between an input terminal and an output terminal. These diodes are connected in parallel, and the cathode of a latter-stage diode is connected to the anode of a former-stage diode through a capacitor. Specifically, from the DC point of view, the diodes are serially connected, and, from the AC point of view, the diodes are connected in parallel through the capacitor.

Abstract: Disclosed is an output overvoltage protection circuit for a power amplifier having a plurality of stages, which comprises a monitor circuit for monitoring an output overvoltage of an output transistor in the final stage of the power amplifier and allowing a current to flow therethrough in response to the monitored output overvoltage, and a current mirror circuit for supplying a current proportional to the current from the monitor circuit in such a manner that the base bias of the first-stage transistor of the power amplifier is reduced in response to the current supplied from the current mirror circuit, to reduce the output of the final-stage output transistor.

Abstract: A printing system is provided capable of preventing unnecessary image information from being sent. The printing system is formed by an image processing apparatus to generate print data and an image forming apparatus to receive the print data and to execute a print. In the printing system, the image forming apparatus includes an image forming; a print mode discriminating section; a confirmation result inputting section; and a request informing section. The image processing apparatus includes a print data generating section; and a selecting and outputting section.

Abstract: A multiplier core outputs a single-phase signal containing a frequency component having a frequency which is an even multiple of the frequency of input signals. A differential amplifier includes first and second nMOS transistors having respective source terminals connected to each other. The output signal from the multiplier core is inputted to the gate terminal of the first nMOS transistor, and the gate terminal of the second nMOS transistor is AC grounded. The differential amplifier differentially amplifies the signals inputted to the gate terminals of the first and second nMOS transistors to output a potential at the drain terminals of the first and second nMOS transistors as a differential signal. The output terminal of the multiplier core is connected through a series LC circuit to the source terminals of the first and second nMOS transistors.

Abstract: A first differential input terminal is connected to one differential output terminal of a VCO, and a second differential input terminal is connected to the other differential output terminal of the VCO. RF signals in a complementary relationship with each other that are output from the VCO are input to the first and second differential input terminals as input signals. The gate of a first N-channel MOS transistor is connected to the first differential input terminal, and the gate of a second N-channel MOS transistors is connected to the second differential input terminal. The sources of the first and second N-channel MOS transistors are connected to a ground potential. The drains of the first and second N-channel MOS transistors are commonly connected to a node.

Abstract: There is provided a valve timing control system for an internal combustion engine, which makes it possible to secure a right amount of combustion gases in a combustion chamber, irrespective of whether an EGR device is in operation or not, thereby obtaining a sufficient effect of reduced exhaust emissions by reduction of NOx. A crank angle position sensor and an intake pipe absolute pressure sensor detect operating conditions of the engine. An ECU determines whether the EGR device is in operation or not. A target cam phase is set in dependence on the detected operating conditions of the engine and a result of the determination as to whether the EGR device is in operation or not, and the cam phase is controlled to the target cam phase.

Abstract: When a jam occurs, a CPU stops reading of compression data, receives again all of the read-out compression data of a page to which the reading-stopped compression data belongs, and stores it into each of corresponding storing areas in a reception buffer again. A time necessary for communication between a host and a printer at the time of jam recovery can be shortened.

Abstract: After detection of contact between respective solder bumps of an electronic component, sucked and held by a suction nozzle of a head tool, and respective solder portions of a circuit board, the solder bumps and the solder portions are melted by heating. Releasing of the electronic component from suction and holding by the suction nozzle of the head tool is performed, not at a time during solder melting, but at a time after the solder is melted, cooled and solidified. Thus, an electronic component mounting method and apparatus capable of mounting high-end electronic components having narrow-pitched bumps are provided.

Abstract: In a driver circuit including transistors each having an emitter follower configuration and a pair of differential transistors with emitter outputs of the transistors of the emitter follower configuration as inputs, end terminals of the pair of differential transistors are connected to individual bonding pads, and the respective bonding pads and voltage sources are individually connected by wires that function as inductors. Thereby, even in the case where the lengths of the wires of output terminals change according to packaging, outputs can be matched by determining the wire lengths of the wires suitably.

Abstract: Disclosed is an output overvoltage protection circuit for a power amplifier having a plurality of stages, which comprises a monitor circuit for monitoring an output overvoltage of an output transistor in the final stage of the power amplifier and allowing a current to flow therethrough in response to the monitored output overvoltage, and a current mirror circuit for supplying a current proportional to the current from the monitor circuit in such a manner that the base bias of the first-stage transistor of the power amplifier is reduced in response to the current supplied from the current mirror circuit, to reduce the output of the final-stage output transistor.

Abstract: A final-stage power amplification transistor is formed of unit transistors arranged in a mixed manner in a region in which the final output amplification transistors for a multi-band power amplifier is formed. Furthermore, an inductance element is connected between output signal lines to which the final output stage transistors are coupled. Thus, the final-stage transistors in a dual band power amplifier can be made free from current concentration due to heat generation without impairing inter-band isolation.

Abstract: The invention has been made to present a diffraction gating that has antireflection function for a broad band of lights and is easy to produce.

Abstract: In a current switching circuit, a complementary circuit switches, in response to an input signal, a pair of current mirror circuits between a first state, enabling the first of the current mirror circuits, through a first current mirror current and disabling the second of the current mirror circuits, and a second state, disabling the first of the current mirror circuits and enabling the second of the current mirror circuits, through a second current, mirror current such that at least one of the first and second current mirror currents flows through a level shift circuit as a level shift current.