Patents by Inventor Kazuya Yamamoto

Kazuya Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120146733
    Abstract: A power amplifier includes an input matching circuit, an amplifier transistor for amplifying an input signal received through the input matching circuit, an element for varying the collector voltage of the amplifier transistor, a bias circuit for varying the idle current in the amplifier transistor, and a compensation circuit for varying capacitance of the input matching circuit to maintain the phase shift and the input reflection in the power amplifier constant when the collector voltage and the idle current are varied, to prevent a decrease in the efficiency of the power amplifier due to changes in the output power of the amplifier transistor.
    Type: Application
    Filed: August 1, 2011
    Publication date: June 14, 2012
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takayuki Matsuzuka, Kazuya Yamamoto, Takao Moriwaki
  • Patent number: 8167302
    Abstract: A sheet of paper is reliably held by suction at the front and rear of a turn guide on the transport path of the sheet according to paper transport conditions.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: May 1, 2012
    Assignees: Duplo Seiko Corporation, Seiko Epson Corporation
    Inventors: Akira Kawaguchi, Kazuya Yamamoto
  • Patent number: 8138836
    Abstract: An emitter-follower bias circuit supplying a bias voltage to the base of an amplification transistor includes: a depletion mode FET boosting a reference voltage; and an emitter-follower circuit generating the bias voltage in response to the reference voltage boosted by the depletion mode FET.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: March 20, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takayuki Matsuzuka, Kazuya Yamamoto, Tomoyuki Asada
  • Publication number: 20120062321
    Abstract: A power amplifier comprises: an amplifying transistor for amplifying an input signal; a reference voltage generating circuit which generates a reference voltage; a bias circuit generating a bias voltage based on the reference voltage and supplying the bias voltage to the amplifying transistor; and a booster elevating an enable voltage input from outside and outputting the enable voltage. The reference voltage generating circuit is turned ON/OFF in correspondence with an output voltage of the booster. The booster includes: an enable terminal to which the enable voltage is applied; a power source terminal connected to a power source; a transistor having a control electrode connected to the enable terminal, a first electrode connected to the power source terminal, and a second electrode that is grounded; and a FET resistor connected between the first electrode of the transistor and the power source terminal. A gate electrode of the FET resistor is open.
    Type: Application
    Filed: April 4, 2011
    Publication date: March 15, 2012
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kazuya Yamamoto, Miyo Miyashita, Satoshi Suzuki, Takayuki Matsuzuka
  • Patent number: 8109510
    Abstract: There is provided a sheet inverting and conveying mechanism for conveying a sheet in a first direction, inverting obverse and reverse sides of the sheet, and then conveying the inverted sheet in a second direction. The mechanism includes: a first conveyance section for receiving, at its conveyance face, one side of the sheet, and for conveying the sheet in the first direction; a sheet inverting section for receiving, at its bent inner peripheral face, one side of the sheet, and for inverting the sheet while bending the sheet along the bent inner peripheral face; and a second conveyance section for receiving, at its conveyance face, one side of the inverted sheet, and for conveying the sheet in the second direction, wherein the first conveyance section and the second conveyance section are formed so that the sheet is conveyed while being attracted to the conveyance faces.
    Type: Grant
    Filed: March 5, 2007
    Date of Patent: February 7, 2012
    Assignee: Duplo Seiko Corporation
    Inventors: Yoshihide Sugiyama, Kazuya Yamamoto
  • Publication number: 20110312192
    Abstract: A film formation method of forming a silicon oxide film on a surface of an object to be processed in a process chamber includes absorbing a seed gas comprising a silane-based gas on the surface of the object to be processed by supplying the seed gas into the process chamber, forming a silicon film having an impurity by supplying a silicon-containing gas as a material gas, and an addition gas including the impurity into the process chamber, and oxidizing the silicon film to convert the silicon film into the silicon oxide film. Accordingly, the silicon oxide film having the high density and the high stress is formed on the surface of the object to be processed.
    Type: Application
    Filed: June 20, 2011
    Publication date: December 22, 2011
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Hiroki MURAKAMI, Kazuhide HASEBE, Kazuya YAMAMOTO, Toshihiko TAKAHASHI, Daisuke SUZUKI
  • Patent number: 8052143
    Abstract: When a sheet of paper is inverted and the direction is changed, members such as a roller do not come into contact with the printed surface of the sheet and it is possible to prevent smudges by eliminating an ink stain on a surface of the sheet.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: November 8, 2011
    Assignees: Duplo Seiko Corporation, Seiko Epson Corporation
    Inventors: Kazuya Yamamoto, Akira Kawaguchi
  • Patent number: 8052142
    Abstract: A turn guide is disposed between a first transport surface and a second transport surface on which a sheet is transported while being sucked. The turn guide has a plurality of guide ribs. The plurality of guide ribs have curved inverting transfer surfaces from an inversion start point corresponding to a first transport surface to an inversion end point corresponding to a second transport surface.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: November 8, 2011
    Assignees: Duplo Seiko Corporation, Seiko Epson Corporation
    Inventors: Yoshihide Sugiyama, Nobuki Tanimoto, Kazuya Yamamoto, Katsunori Takahashi
  • Patent number: 8052146
    Abstract: Provided is a sheet inverting apparatus wherein members, such as a roller, are not brought into contact with the printed surface of a sheet at all, and the occurrence of dirt can be prevented by eliminating friction of ink on the surface of the sheet. A first transport apparatus and a second transport apparatus each have a plurality of transport belts which move on transport tracks along sheet transport directions and a suction box which sucks the sheet on the transport belts through suction holes formed on the transport belts. A turn guide arranged between the first transport apparatus and the second transport apparatus has a plurality of guide ribs disposed between the transport belts. Each of the guide ribs coming into slidable contact with the sheet forms a curved inverting transfer surface from an inversion starting point side to an inversion end point side.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: November 8, 2011
    Assignees: Duplo Seiko Corporation, Seiko Epson Corporation
    Inventors: Yoshihide Sugiyama, Kazuya Yamamoto, Katsunori Takahashi, Hidemasa Kanada, Junichi Kakuta
  • Patent number: 8049483
    Abstract: A reference voltage generation circuit comprises: a first depletion mode FET; a second depletion mode FET; a first resistor; a first bipolar transistor; a second resistor; a second bipolar transistor; a third bipolar transistor; a third resistor; a third depletion mode FET having its drain connected to a second end of the first resistor and to the collector of the first bipolar transistor; and a fourth bipolar transistor having its base and collector connected to the gate and the source of the third depletion mode FET, and its emitter grounded, wherein source voltage of the second depletion mode FET is output as a reference voltage.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: November 1, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazuya Yamamoto, Miyo Miyashita
  • Patent number: 7993705
    Abstract: A method for using a film formation apparatus includes performing film formation of a product film selected from the group consisting of a silicon nitride film and a silicon oxynitride film on a target substrate within a reaction chamber of the film formation apparatus; and unloading the target substrate from the reaction chamber. Thereafter, the method includes first heating an inner surface of the reaction chamber at a post process temperature while supplying a post process gas for nitridation into the reaction chamber, thereby performing nitridation of a by-product film deposited on the inner surface of the reaction chamber; then rapidly cooling the inner surface of the reaction chamber, thereby cracking the by-product film by a thermal stress; and then forcibly exhausting gas from inside the reaction chamber to carry the by-product film, thus peeled off from the inner surface.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: August 9, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Nobutake Nodera, Kazuhide Hasebe, Kazuya Yamamoto
  • Publication number: 20110187459
    Abstract: An emitter-follower bias circuit supplying a bias voltage to the base of an amplification transistor includes: a depletion mode FET boosting a reference voltage; and an emitter-follower circuit generating the bias voltage in response to the reference voltage boosted by the depletion mode FET.
    Type: Application
    Filed: September 3, 2010
    Publication date: August 4, 2011
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takayuki Matsuzuka, Kazuya Yamamoto, Tomoyuki Asada
  • Publication number: 20110187349
    Abstract: A detector circuit for detecting degradation in the distortion characteristics of a power amplifier based on signals from both ends of a coupled line of a directional coupler. The detector circuit includes a phase shifter/attenuator for phase shifting and attenuating a signal from a coupled terminal of the coupled line, a differential amplifier for outputting difference between an output signal from the phase shifter/attenuator and a signal from the isolated terminal of the coupled line, a wave detector circuit for converting the difference into a DC signal, and a comparing circuit for determining whether the voltage level of the DC signal exceeds a predetermined level. When degradation in the distortion characteristics of the power amplifier arises, the phase shifter/attenuator phase shifts the signal from the coupled terminal and outputs a signal 180° out of phase with the signal from the isolated terminal.
    Type: Application
    Filed: November 8, 2010
    Publication date: August 4, 2011
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kazuya Yamamoto, Tomoyuki Asada, Miyo Miyashita
  • Patent number: 7936219
    Abstract: A power amplifier and bias circuit includes a combination circuit in which a voltage drive bias circuit and a current drive bias circuit are connected in a parallel relationship with each other. The power amplifier bias circuit also includes an idle current control circuit which uses the collector voltage of amplifier transistors. When the collector voltage of the amplifier transistors is lower than the threshold voltage of a first transistor (approximately 1.3 V), the first transistor is turned off. At that time, since the reference voltage (2.4-2.5 V) is higher than the voltage for turning on both a second transistor and a diode (namely, approximately 1.3 V plus 0.7 V), a current flows and the first transistor turns on. As a result, a current is drawn from the bases of the amplifier transistors to GND through two resistances, so that the idle currents of the amplifier transistors decrease.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: May 3, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takayuki Matsuzuka, Kazuya Yamamoto, Atsushi Okamura
  • Patent number: 7928804
    Abstract: A power amplifier includes: a semiconductor substrate; a preceding-stage amplifying device on the semiconductor substrate, amplifying an input signal; a following-stage amplifying device on the semiconductor substrate, amplifying an output signal of the preceding-stage amplifying device; and an inter-stage matching circuit connecting the preceding-stage amplifying device to the following-stage amplifying device. The preceding-stage amplifying device has a first field effect transistor; the following-stage amplifying device has a heterojunction bipolar transistor; and the inter-stage matching circuit has a capacitance galvanically separating the output terminal of the preceding-stage amplifying device from the input terminal of the following-stage amplifying device.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: April 19, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazuya Yamamoto, Satoshi Suzuki, Takao Haruna, Takao Moriwaki
  • Patent number: 7918449
    Abstract: A double-sided image forming device includes: a paper feeding section (3); a printing section (4); a first conveyance route (6) for conveying a fed paper sheet (2) to a paper discharge section (8) via the printing section (4); and a second conveyance route (7) for receiving, on its conveyance surface, the paper sheet (2), a first side (21) of which has been printed, from the first conveyance route (6), and for conveying the paper sheet (2) while reversing it, thereby conveying the paper sheet (2) to the upstream side of the printing section (4) in the conveyance direction of the first conveyance route (6), wherein the second conveyance route (7) has a reverse conveyance route (9) for receiving, on its conveyance surface, a second side (22) of the paper sheet (2), and for conveying the paper sheet (2) while reversing it, and wherein the reverse conveyance route (9) is formed by a combination of a plurality of reverse mechanisms each including: a first conveyance section (91) for linearly conveying the paper sh
    Type: Grant
    Filed: April 18, 2007
    Date of Patent: April 5, 2011
    Assignee: Duplo Seiko Corporation
    Inventors: Yoshihide Sugiyama, Kazuya Yamamoto
  • Patent number: 7907032
    Abstract: A directional coupler includes a main line connected at a first end to an input port and at a second end to an output port, a coupled line connected at a first end to a coupled port and at a second end to an isolated port, and a phase shifter connected at a first end to the isolated port and at a second end to the coupled port. The phase shifter phase shifts a second reflected wave component such that the second reflected wave component is opposite in phase to a first reflected wave component, the second reflected wave component traveling from the output port to the coupled port through the isolated port and the phase shifter, the first reflected wave component traveling from the output port to the coupled port through the coupled line.
    Type: Grant
    Filed: May 13, 2009
    Date of Patent: March 15, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazuya Yamamoto, Miyo Miyashita
  • Publication number: 20110057746
    Abstract: A directional coupler includes capacitive elements electrically connected to a coupled port and an isolated port, respectively, for a coupled line on a chip (on-chip). The capacitive elements serve as matching capacitive elements and may be MIM (Metal Insulator Metal) capacitors on a substrate. A first end of a first of the capacitive elements is connected between the coupled port and the coupled line and a second end is grounded. A first end of a second of the capacitive elements is connected between the isolated port and the coupled line and a second end is grounded.
    Type: Application
    Filed: May 18, 2010
    Publication date: March 10, 2011
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kazuya Yamamoto, Miyo Miyashita, Hitoshi Kurusu, Tomoyuki Asada
  • Patent number: 7880917
    Abstract: When a jam occurs, a CPU stops reading of compression data, receives again all of the read-out compression data of a page to which the reading-stopped compression data belongs, and stores it into each of corresponding storing areas in a reception buffer again. A time necessary for communication between a host and a printer at the time of jam recovery can be shortened.
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: February 1, 2011
    Assignee: Oki Data Corporation
    Inventor: Kazuya Yamamoto
  • Publication number: 20110018639
    Abstract: A power amplifier and bias circuit includes a combination circuit in which a voltage drive bias circuit and a current drive bias circuit are connected in a parallel relationship with each other. The power amplifier bias circuit also includes an idle current control circuit which uses the collector voltage of amplifier transistors. When the collector voltage of the amplifier transistors is lower than the threshold voltage of a first transistor (approximately 1.3 V), the first transistor is turned off. At that time, since the reference voltage (2.4-2.5 V) is higher than the voltage for turning on both a second transistor and a diode (namely, approximately 1.3 V plus 0.7 V), a current flows and the first transistor turns on. As a result, a current is drawn from the bases of the amplifier transistors to GND through two resistances, so that the idle currents of the amplifier transistors decrease.
    Type: Application
    Filed: February 25, 2010
    Publication date: January 27, 2011
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takayuki Matsuzuka, Kazuya Yamamoto, Atsushi Okamura