Abstract: A semiconductor device is disclosed, which comprises a semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate, the interlayer insulating film comprising a first insulating film and a second insulating film formed on the first insulating film, the first insulating film comprising a silicon oxide film containing carbon of a concentration, the second insulating film comprising a silicon oxide film containing carbon of a concentration lower than the concentration of the first insulating film or comprising a silicon oxide film containing substantially no carbon, a via contact made of a metal material embedded in a via hole formed in the interlayer insulating film, a diameter of the via hole in the first insulating film being smaller than that in the second insulating film at an interface between the first insulating film and the second insulating film.

Abstract: A semiconductor device according to an embodiment of the present invention includes a plurality of chip regions and a plurality of chip rings. The plurality of chip regions include semiconductor integrated circuits each having a multilayered wiring structure using a metal wiring, and are formed into independent chips. The plurality of chip rings has the multilayered wiring structure using the metal wiring, and surround the respective chip regions. The plurality of chip rings are electrically connected to one another.

Abstract: A drive circuit for a voltage driven type semiconductor element, includes: an electrical charge discharge unit that discharges electrical charge from a gate terminal of a voltage driven type semiconductor element when the voltage driven type semiconductor element is turned OFF; and an electrical discharge control unit that detects a time variation of a collector voltage of the voltage driven type semiconductor element, and controls electric discharge by the electrical charge discharge unit according to the time variation of the collector voltage which has been detected.

Abstract: A prismatic battery case with high dimensional precision is manufactured, while pursuing an improvement in productivity, with a manufacturing method of a prismatic battery case that includes a first step for molding an intermediate cup body (8) by impact molding a pellet (7) of prescribed shape, and a second step for molding a prismatic battery case (9) with a cross section of substantially rectangular shape by DI processing the intermediate cup body (8). The DI processing conducts drawing and ironing continuously, in one action.

Abstract: There is here disclosed a manufacturing method of a semiconductor device, comprising providing a first film by a PVD process in a recess formed in at least one insulating film, the first film containing at least one metal element belonging to any one of the groups 4-A, 5-A, and 6-A, continuously providing a second film by at least one of CVD and ALD processes on the first film without opening to atmosphere, the second film containing at least one metal element belonging to any one of the groups 4-A, 5-A, and 6-A, continuously providing a third film by the PVD process on the second film without opening to the atmosphere, the third film containing at least one metal element belonging to any one of the groups 4-A, 5-A, and 6-A, continuously providing a first Cu film on the third film without opening to the atmosphere, and heating the Cu film.

Abstract: A semiconductor device has an active element structure formed on a semiconductor substrate. A first insulating film is provided above the semiconductor substrate. A first interconnect layer composed of copper is provided in a surface of the first insulating film. A second insulating film is provided on the first insulating film. A connection hole is formed in the second insulating film and has its bottom connected to the first insulating layer. A connection plug composed of a single crystal of copper is filled in the connection hole so that no other crystals of copper are provided in the connection hole. An interconnect trench is formed in a surface of the second insulating film and has its bottom connected to the connection hole. A second interconnect layer is provided in the interconnect trench.

Abstract: Battery case for containing electrode assembly and electrolyte of electroltic battery has a grid on at least a portion of an inner surface of the case, formed by intersecting pluralities of first and second ridges. The grid enables construction of a battery case of minimal thickness while having high strength and rigidity, and resistance to deformation caused by generation of higher internal battery pressure during use.

Abstract: A semiconductor device includes an active element structure that is formed on a semiconductor substrate and has a connection region formed in the surface of the semiconductor substrate. A contact hole extends from a surface of a first insulating film formed on the semiconductor substrate to the connection region. A contact plug is provided in the contact hole. A clearance formed in the contact plug is formed with a buried conductive film consisting of a material different from the contact plug. The buried conductive film has a continuous surface without forming a step with the surface of the contact plug.

Abstract: A semiconductor device includes at least first and second lower layer wirings provided on a surface of an insulator on a semiconductor substrate, a first interlayer film provided on the insulator to cover surfaces of the first and second lower layer wirings, first and second connection wirings which are provided on the first interlayer film and include first and second films contacting the first and second lower layer wirings respectively, and a plate electrode which is continuously provided on the second connection wiring and includes at least the first film.

Abstract: A semiconductor device manufacturing method comprises forming a first insulating film including silicon, carbon, nitrogen, and hydrogen above a substrate in a first chamber, carrying the substrate into a second chamber other than the first chamber, and discharging a rare gas in the second chamber, and forming a second insulating film including silicon, carbon, oxygen, and hydrogen above the first insulating film after the discharging the rare gas.

Abstract: A semiconductor device is disclosed, which comprises a semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate, the interlayer insulating film comprising a first insulating film and a second insulating film formed on the first insulating film, the first insulating film comprising a silicon oxide film containing carbon of a concentration, the second insulating film comprising a silicon oxide film containing carbon of a concentration lower than the concentration of the first insulating film or comprising a silicon oxide film containing substantially no carbon, a via contact made of a metal material embedded in a via hole formed in the interlayer insulating film, a diameter of the via hole in the first insulating film being smaller than that in the second insulating film at an interface between the first insulating film and the second insulating film.

Abstract: A plurality of wiring layers are laminated on an LSI chip. Each wiring layer includes an electrode to which is applied a mechanical pressure, a first insulating film formed in a region where it is necessary to have a high mechanical strength and having the electrode formed therein, a second insulating film formed in the same layer as the layer of the first insulating film and formed in a region where a mechanical strength higher than that of the first insulating layer is not required, and a wiring layer formed on the surface of the second insulating film.

Abstract: In a semiconductor device fabrication method, a first low dielectric constant film having a specific dielectric constant of k less than 3 (k<3) is formed over a wafer so that an edge position of the first low dielectric constant film aligns with a first position along the circumference of the wafer. Then, a first protection layer having a gas permeability lower than that of the first low dielectric constant film is formed over the first low dielectric constant film and the wafer so that an edge of the first protection layer aligns with a second position that is located outside the first position. Then, a second low dielectric constant film having a specific dielectric constant of k less than 3 (k<3) is formed over the first protection layer so that an edge of the second low dielectric constant film is located at the first position.

Abstract: A plurality of wiring layers are laminated on an LSI chip. Each wiring layer includes an electrode to which is applied a mechanical pressure, a first insulating film formed in a region where it is necessary to have a high mechanical strength and having the electrode formed therein, a second insulating film formed in the same layer as the layer of the first insulating film and formed in a region where a mechanical strength higher than that of the first insulating layer is not required, and a wiring layer formed on the surface of the second insulating film.

Abstract: In a semiconductor device fabrication method, a first low dielectric constant film having a specific dielectric constant of k less than 3 (k<3) is formed over a wafer so that an edge position of the first low dielectric constant film aligns with a first position along the circumference of the wafer. Then, a first protection layer having a gas permeability lower than that of the first low dielectric constant film is formed over the first low dielectric constant film and the wafer so that an edge of the first protection layer aligns with a second position that is located outside the first position.

Abstract: In a semiconductor device fabrication method, a first low dielectric constant film having a specific dielectric constant of k less than 3 (k<3) is formed over a wafer so that an edge position of the first low dielectric constant film aligns with a first position along the circumference of the wafer. Then, a first protection layer having a gas permeability lower than that of the first low dielectric constant film is formed over the first low dielectric constant film and the wafer so that an edge of the first protection layer aligns with a second position that is located outside the first position. Then, a second low dielectric constant film having a specific dielectric constant of k less than 3 (k<3) is formed over the first protection layer so that an edge of the second low dielectric constant film is located at the first position.

Abstract: A plurality of wiring layers are laminated on an LSI chip. Each wiring layer includes an electrode to which is applied a mechanical pressure, a first insulating film formed in a region where it is necessary to have a high mechanical strength and having the electrode formed therein, a second insulating film formed in the same layer as the layer of the first insulating film and formed in a region where a mechanical strength higher than that of the first insulating layer is not required, and a wiring layer formed on the surface of the second insulating film.

Abstract: A semiconductor device includes at least first and second lower layer wirings provided on a surface of an insulator on a semiconductor substrate, a first interlayer film provided on the insulator to cover surfaces of the first and second lower layer wirings, first and second connection wirings which are provided on the first interlayer film and include first and second films contacting the first and second lower layer wirings respectively, and a plate electrode which is continuously provided on the second connection wiring and includes at least the first film.

Abstract: The present invention is a method of producing a semiconductor device in which at least one alignment mark to be used in an exposure process of a lithographic process is formed of a wiring material which is copper or includes copper as a main component, and the alignment mark is formed entirely in an area outside an area where dicing is to be executed.

Abstract: A semiconductor manufacturing method has the steps of preparing an SOI substrate having a supporting substrate, an insulating film formed above the supporting substrate, a semiconductor region formed above the insulating film, and an intermediate layer formed between the supporting substrate and the insulating film, forming a semiconductor element in the semiconductor region, and removing the intermediate layer to separate the supporting substrate and the semiconductor region in which the semiconductor element is formed.