Patents by Inventor Kazuyuki Higashi

Kazuyuki Higashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150255985
    Abstract: A vehicle-to-grid system connected to a power grid includes a first vehicle group of one or more vehicles connected to the power grid, a second vehicle group of one or more vehicles connected to the power grid, and a vehicle-to-grid controller. The vehicle-to-grid controller causes each vehicle from the second vehicle group to supply electrical power to the power grid at a nominal frequency and at an adjusted amplitude, and causes each vehicle from the first vehicle group to supply electrical power to the power grid at an adjusted frequency that is different than the nominal frequency and at a nominal amplitude that is different than the adjusted amplitude.
    Type: Application
    Filed: March 5, 2014
    Publication date: September 10, 2015
    Applicant: Nissan North America, Inc.
    Inventor: Kazuyuki Higashi
  • Publication number: 20150256012
    Abstract: A method of charging a battery in a charging system having a power convertor that converts AC electrical power to DC electrical power, the method comprising generating a carrier signal having a carrier frequency that continuously varies between a minimum carrier frequency value and a maximum carrier frequency value, and operating a switching component of the power convertor using the carrier signal.
    Type: Application
    Filed: March 7, 2014
    Publication date: September 10, 2015
    Applicant: NISSAN NORTH AMERICA, INC.
    Inventor: Kazuyuki Higashi
  • Publication number: 20150255373
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device comprises forming through holes extending through a semiconductor substrate in a thickness direction to integrated circuits in chip areas, and forming a first mark opening and second mark openings in a dicing line. The method detects the first mark opening based on positions of the second mark openings. Then, the method performs alignment of exposure positions based on the position of the first mark opening to perform photolithography, thereby forming a resist pattern on the back side of the semiconductor substrate.
    Type: Application
    Filed: June 27, 2014
    Publication date: September 10, 2015
    Inventors: Shinya WATANABE, Kazuyuki HIGASHI, Taku KAMOTO
  • Patent number: 9123717
    Abstract: According to one embodiment, a semiconductor device manufacturing method includes: bonding a first wafer and a second wafer to each other, to form a stack; rubbing a film attached with a fill material in a thin-film shape into a gap located between a bevel of the first wafer and a bevel of the second wafer, to fill the gap with the fill material; and thinning the first wafer.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: September 1, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenro Nakamura, Mitsuyoshi Endo, Kazuyuki Higashi, Takashi Shirono
  • Publication number: 20150214134
    Abstract: According to an embodiment, a semiconductor device is provided. The semiconductor device includes a through-hole, a copper layer, and a metal portion. The through-hole penetrates a semiconductor substrate between front and rear sides. The copper layer is formed inside the through-hole. The metal portion is made of a metal other than copper, formed closer to a hole core side of the through-hole than the copper layer is, and involves a void therein.
    Type: Application
    Filed: September 10, 2014
    Publication date: July 30, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Koji OGISO, Kazuyuki HIGASHI, Tatsuo MIGITA
  • Publication number: 20150123286
    Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a first conductive member formed on the semiconductor substrate; a first insulating film formed on the same layer as the first conductive member; a second conductive member formed so as to contact with a portion of an upper surface of the first conductive member; a second insulating film formed on the first insulating film so as to contact with a portion of the upper surface of the first conductive member, and including at least one type of element among elements contained in the first insulating film except Si; and an etching stopper film formed on the second insulating film so as to contact with a portion of a side surface of the second conductive member, and having an upper edge located below the upper surface of the second conductive member.
    Type: Application
    Filed: January 15, 2015
    Publication date: May 7, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Makoto WADA, Kazuyuki HIGASHI
  • Patent number: 9018696
    Abstract: A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The plurality of first conductive layers comprises a stepped portion formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The wiring comprises a plurality of second conductive layers extending upwardly from an upper surface of the first conductive layers comprising the stepped portion. The plurality of second conductive layers are formed such that upper ends thereof are aligned with a surface parallel to the substrate, and such that a diameter thereof decreases from the upper end thereof to a lower end thereof. The plurality of second conductive layers are formed such that the greater a length thereof in the perpendicular direction, the larger a diameter of the upper end thereof.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: April 28, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Wada, Kazuyuki Higashi, Naofumi Nakamura, Tsuneo Uenaka
  • Publication number: 20150108648
    Abstract: A semiconductor device includes first and second semiconductor members and a first barrier film. The first semiconductor member includes a first insulating film, and a first wiring film in the first insulating film, the surface of which is exposed in the first insulating film. The second semiconductor member includes a second insulating film, and a second wiring film in the second insulating film, the surface of which is exposed in the second insulating film. The first barrier film forms a barrier to diffusion of the material of the first wiring film into the second insulating film and is formed of a compound of metal element of the first wiring film and an element of the second insulating film in a region where the first wiring film and the second insulating film are in contact with each other at the junction interface of the first and second semiconductor members.
    Type: Application
    Filed: September 2, 2014
    Publication date: April 23, 2015
    Inventors: Kazumichi TSUMURA, Kazuyuki HIGASHI
  • Publication number: 20150054172
    Abstract: According to one embodiment, a semiconductor device includes an integrated circuit and a conductive material. The integrated circuit is provided on a surface of a semiconductor layer. The conductive material is embedded into a via which penetrates the semiconductor layer in a thickness direction thereof and is electrically connected to the integrated circuit. The conductive material includes a contact portion and a through portion, and the contact portion includes a cross-sectional area that is greater than a cross-sectional area of the through portion.
    Type: Application
    Filed: March 2, 2014
    Publication date: February 26, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takashi SHIRONO, Kazuyuki HIGASHI, Shinya WATANABE, Tatsuo MIGITA
  • Patent number: 8963319
    Abstract: According to one embodiment, a semiconductor chip includes a semiconductor substrate, a via and an insulating layer. The semiconductor substrate has a first major surface and a second major surface on opposite side from the first major surface. The semiconductor substrate is provided with a circuit section including an element and a wiring and a guard ring structure section surrounding the circuit section on the first major surface side. The via is provided in a via hole extending from the first major surface side to the second major surface side of the semiconductor substrate. The insulating layer is provided in a first trench extending from the first major surface side to the second major surface side of the semiconductor substrate.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: February 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumichi Tsumura, Kazuyuki Higashi
  • Patent number: 8916417
    Abstract: After stacking m wafers in each of which a plurality of semiconductor chips are formed, the m wafers are diced to semiconductor chips to form a first chip stack having m of the semiconductor chips stacked, and, after stacking n wafers, the n wafers are diced to semiconductor chips to form a second chip stack having n of the semiconductor chips stacked. Next, the first chip stack is sorted according to the number of defective semiconductor chips included in the first chip stack, and the second chip stack is sorted according to the number of defective semiconductor chips included in the second chip stack. Furthermore, the first chip stack or the second chip stack after sorting are combined to form a third chip stack.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: December 23, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuyuki Higashi, Yoshiaki Sugizaki
  • Patent number: 8912060
    Abstract: A method for manufacturing a semiconductor device includes: forming a first layer on a substrate; forming a first contact hole in the first layer; burying a sacrificial film in the first contact hole; forming a second layer on the first layer and the first contact hole after burying; forming a second contact hole reaching the sacrificial film in the second layer; removing the sacrificial film from the first contact hole via the second contact hole; and providing a contact electrode in the first contact hole and the second contact hole.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: December 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuneo Uenaka, Kazuyuki Higashi
  • Patent number: 8907493
    Abstract: A first through hole 16 and a second through hole 17 are formed which penetrate from a rear surface 10a side of an element formation surface 10b of a semiconductor substrate (silicon substrate 10) in which an element section Ra is formed, to the element formation surface. An outer circumference insulation film 12 is formed on the side wall of the bottom of the second through hole 17 to surround the outer circumference of the second through hole 17 having a larger opening diameter among these through holes.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: December 9, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kengo Uchida, Kazuyuki Higashi
  • Publication number: 20140264718
    Abstract: A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The plurality of first conductive layers comprises a stepped portion formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The wiring comprises a plurality of second conductive layers extending upwardly from an upper surface of the first conductive layers comprising the stepped portion. The plurality of second conductive layers are formed such that upper ends thereof are aligned with a surface parallel to the substrate, and such that a diameter thereof decreases from the upper end thereof to a lower end thereof. The plurality of second conductive layers are formed such that the greater a length thereof in the perpendicular direction, the larger a diameter of the upper end thereof.
    Type: Application
    Filed: May 30, 2014
    Publication date: September 18, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Makoto WADA, Kazuyuki HIGASHI, Naofumi NAKAMURA, Tsuneo UENAKA
  • Publication number: 20140242779
    Abstract: According to one embodiment, a semiconductor device manufacturing method includes: bonding a first wafer and a second wafer to each other, to form a stack; rubbing a film attached with a fill material in a thin-film shape into a gap located between a bevel of the first wafer and a bevel of the second wafer, to fill the gap with the fill material; and thinning the first wafer.
    Type: Application
    Filed: July 30, 2013
    Publication date: August 28, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenro NAKAMURA, Mitsuyoshi ENDO, Kazuyuki HIGASHI, Takashi SHIRONO
  • Patent number: 8759983
    Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a connecting member formed above the semiconductor substrate configured to electrically connect upper and lower conductive members; a first insulating film formed in the same layer as the connecting member; a wiring formed on the connecting member, the wiring including a first region and a second region, the first region contacting with a portion of an upper surface of the connecting member, and the second region located on the first region and having a width greater than that of the first region; and a second insulating film formed on the first insulating film so as to contact with at least a portion of the first region of the wiring and with a bottom surface of the second region.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: June 24, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Wada, Akihiro Kajita, Kazuyuki Higashi
  • Patent number: 8759162
    Abstract: A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The plurality of first conductive layers comprises a stepped portion formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The wiring comprises a plurality of second conductive layers extending upwardly from an upper surface of the first conductive layers comprising the stepped portion. The plurality of second conductive layers are formed such that upper ends thereof are aligned with a surface parallel to the substrate, and such that a diameter thereof decreases from the upper end thereof to a lower end thereof. The plurality of second conductive layers are formed such that the greater a length thereof in the perpendicular direction, the larger a diameter of the upper end thereof.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: June 24, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Wada, Kazuyuki Higashi, Naofumi Nakamura, Tsuneo Uenaka
  • Patent number: 8754532
    Abstract: A semiconductor device includes a supporting substrate; a semiconductor substrate that includes a first surface in which at least one layer is formed and a second surface that is positioned on an opposite side to the first surface, and is pasted to a surface of the supporting substrate with adhesive such that the first surface faces the supporting substrate side; a protective film that is formed on the second surface of the semiconductor substrate and on a surface of the adhesive extending outwardly from a region between the supporting substrate and the semiconductor substrate, and including a perimeter part that is positioned outside a perimeter part of the adhesive, and positioned inside a perimeter part of the supporting substrate; and an electrode material that is formed so as to be embedded in a penetration hole that penetrates the protective film and the semiconductor substrate.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: June 17, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumichi Tsumura, Kazuyuki Higashi
  • Patent number: 8680604
    Abstract: A first region comprises: a semiconductor layer including a columnar portion, a charge storage layer, and a plurality of first conductive layers. The second region comprises: a plurality of second conductive layers formed in the same layer as the plurality of first conductive layers. The plurality of first conductive layers configure a stepped portion at an end vicinity of the first region. The stepped portion is formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The plurality of second conductive layers is formed such that positions of ends thereof at an end vicinity of the second region surrounding the first region are aligned in substantially the perpendicular direction to the substrate.
    Type: Grant
    Filed: February 16, 2010
    Date of Patent: March 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuyuki Higashi, Tsuneo Uenaka
  • Publication number: 20140054774
    Abstract: A first through hole 16 and a second through hole 17 are formed which penetrate from a rear surface 10a side of an element formation surface 10b of a semiconductor substrate (silicon substrate 10) in which an element section Ra is formed, to the element formation surface. An outer circumference insulation film 12 is formed on the side wall of the bottom of the second through hole 17 to surround the outer circumference of the second through hole 17 having a larger opening diameter among these through holes.
    Type: Application
    Filed: February 7, 2013
    Publication date: February 27, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kengo UCHIDA, Kazuyuki HIGASHI