Patents by Inventor Kazuyuki Higashi
Kazuyuki Higashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME, AND MANAGEMENT SYSTEM OF SEMICONDUCTOR DEVICE
Publication number: 20130234339Abstract: After stacking m wafers in each of which a plurality of semiconductor chips are formed, the m wafers are diced to semiconductor chips to form a first chip stack having m of the semiconductor chips stacked, and, after stacking n wafers, the n wafers are diced to semiconductor chips to form a second chip stack having n of the semiconductor chips stacked. Next, the first chip stack is sorted according to the number of defective semiconductor chips included in the first chip stack, and the second chip stack is sorted according to the number of defective semiconductor chips included in the second chip stack. Furthermore, the first chip stack or the second chip stack after sorting are combined to form a third chip stack.Type: ApplicationFiled: August 31, 2012Publication date: September 12, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazuyuki HIGASHI, Yoshiaki Sugizaki -
Patent number: 8426908Abstract: A nonvolatile semiconductor memory device includes a first region having a plurality of electrically rewritable memory cells disposed therein, and a second region adjacent to the first region. The nonvolatile semiconductor memory device includes a plurality of first conductive layers, a semiconductor layer, a charge storage layer, and an insulating columnar layer. The plurality of first conductive layers are stacked in the first region and the second region, and include a stepped portion in the second region, positions of ends of the plurality of first conductive layers being different in the stepped portion. The semiconductor layer is surrounded by the first conductive layers in the first region, includes a first columnar portion extending in a stacking direction. The charge storage layer is formed between the first conductive layers and a side surface of the first columnar portion.Type: GrantFiled: September 3, 2010Date of Patent: April 23, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Kazuyuki Higashi
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Patent number: 8405141Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, an insulating film, a non-doped semiconductor film, a semiconductor pillar, a charge storage film, a contact, and a spacer insulating film. The stacked body is provided on the substrate. The stacked body includes a plurality of doped semiconductor films stacked. The insulating film is provided between the doped semiconductor films in a first region. The non-doped semiconductor film is provided between the doped semiconductor films in a second region. The semiconductor pillar pierces the stacked body in a stacking direction of the stacked body in the first region. The charge storage film is provided between the doped semiconductor film and the semiconductor pillar. The contact pierces the stacked body in the stacking direction in the second region. The spacer insulating film is provided around the contact.Type: GrantFiled: September 3, 2010Date of Patent: March 26, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Toru Matsuda, Kazuyuki Higashi
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Patent number: 8405142Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a multilayer body, a semiconductor member and a charge storage layer. The multilayer body is provided on the substrate, with a plurality of insulating films and electrode films alternately stacked, and includes a first staircase and a second staircase opposed to each other. The semiconductor member is provided in the multilayer body outside a region provided with the first staircase and the second staircase, and the semiconductor member extends in stacking direction of the insulating films and the electrode films. The charge storage layer is provided between each of the electrode films and the semiconductor member. The each of the electrode films includes a first terrace formed in the first staircase, a second terrace formed in the second staircase and a bridge portion connecting the first terrace and the second terrace.Type: GrantFiled: March 9, 2011Date of Patent: March 26, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Ryota Katsumata, Kazuyuki Higashi, Yoshiaki Fukuzumi
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Patent number: 8390055Abstract: A memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The semiconductor layer includes a columnar portion that extends in a perpendicular direction to a substrate. The charge storage layer is formed around a side surface of the columnar portion. The plurality of first conductive layers are formed around the side surface of the columnar portion and the charge storage layer. A control circuit comprises a plurality of second conductive layers, an insulating layer, and a plurality of plug layers. The plurality of second conductive layers are formed in the same layers as the plurality of first conductive layers. The insulating layer is formed penetrating the plurality of second conductive layers in the perpendicular direction. The plurality of plug layers are formed penetrating the insulating layer in the perpendicular direction.Type: GrantFiled: September 15, 2010Date of Patent: March 5, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Kazuyuki Higashi, Tadashi Iguchi
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Patent number: 8350387Abstract: A semiconductor storage device includes a memory cell transistor and a selective transistor formed on a semiconductor substrate, a first interlayer insulating film which is formed on the semiconductor substrate, an insulating layer formed by use of a material higher in dielectric constant than the first interlayer insulating film, a contact plug which penetrates the insulating layer and the first interlayer insulating film and which is electrically connected to a drain of the selective transistor, and a bit line which is in contact with the contact plug. A partial region in the bottom surface of the bit line is located lower than the upper surface of the contact plug, and is in contact with the surface of the insulating layer, and the partial region is also in contact with the side surface of the contact plug.Type: GrantFiled: August 27, 2008Date of Patent: January 8, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Kanae Uchida, Masato Endo, Kazuyuki Higashi
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Publication number: 20120319296Abstract: According to one embodiment, a semiconductor chip includes a semiconductor substrate, a via and an insulating layer. The semiconductor substrate has a first major surface and a second major surface on opposite side from the first major surface. The semiconductor substrate is provided with a circuit section including an element and a wiring and a guard ring structure section surrounding the circuit section on the first major surface side. The via is provided in a via hole extending from the first major surface side to the second major surface side of the semiconductor substrate. The insulating layer is provided in a first trench extending from the first major surface side to the second major surface side of the semiconductor substrate.Type: ApplicationFiled: March 14, 2012Publication date: December 20, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Kazumichi Tsumura, Kazuyuki Higashi
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Publication number: 20120152168Abstract: A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a metal film on the insulating film at a second substrate temperature lower than the first substrate temperature, and oxidizing at least part of the metal film with oxidizing species remaining in the insulating film.Type: ApplicationFiled: February 29, 2012Publication date: June 21, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Atsuko Sakata, Junichi Wada, Seiichi Omoto, Masaaki Hatano, Soichi Yamashita, Kazuyuki Higashi, Naofumi Nakamura, Masaki Yamada, Kazuya Kinoshita, Tomio Katata, Masahiko Hasunuma
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Patent number: 8169016Abstract: A plurality of conductive layers are stacked in a first region and a second region. A semiconductor layer is surrounded by the conductive layers in the first region, includes a columnar portion extending in a perpendicular direction with respect to a substrate. A charge storage layer is formed between the conductive layers and a side surface of the columnar portion. The conductive layers includes first trenches, second trenches, and third trenches. The first trenches are arranged in the first region so as to have a first pitch in a first direction. The second trenches are arranged in the second region so as to have a second pitch in the first direction. The third trenches are arranged in the second region so as to have a third pitch in the first direction and so as to be sandwiched by the second trenches.Type: GrantFiled: September 2, 2010Date of Patent: May 1, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Kazuyuki Higashi
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Patent number: 8148274Abstract: A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a metal film on the insulating film at a second substrate temperature lower than the first substrate temperature, and oxidizing at least part of the metal film with oxidizing species remaining in the insulating film.Type: GrantFiled: January 24, 2008Date of Patent: April 3, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Junichi Wada, Atsuko Sakata, Seiichi Omoto, Masaaki Hatano, Soichi Yamashita, Kazuyuki Higashi, Naofumi Nakamura, Masaki Yamada, Kazuya Kinoshita, Tomio Katata, Masahiko Hasunuma
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Publication number: 20120068252Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a multilayer body, a semiconductor member and a charge storage layer. The multilayer body is provided on the substrate, with a plurality of insulating films and electrode films alternately stacked, and includes a first staircase and a second staircase opposed to each other. The semiconductor member is provided in the multilayer body outside a region provided with the first staircase and the second staircase, and the semiconductor member extends in stacking direction of the insulating films and the electrode films. The charge storage layer is provided between each of the electrode films and the semiconductor member. The each of the electrode films includes a first terrace formed in the first staircase, a second terrace formed in the second staircase and a bridge portion connecting the first terrace and the second terrace.Type: ApplicationFiled: March 9, 2011Publication date: March 22, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Ryota KATSUMATA, Kazuyuki HIGASHI, Yoshiaki FUKUZUMI
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Publication number: 20120061743Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, a contact, a semiconductor member, a charge storage layer, and a penetration member. The stacked body includes an electrode film stacked alternately with an insulating film. A configuration of an end portion of the stacked body is a stairstep configuration having a step provided every electrode film. The contact is connected to the electrode film from above the end portion. The semiconductor member is provided in a portion of the stacked body other than the end portion to pierce the stacked body in a stacking direction. The charge storage layer is provided between the electrode film and the semiconductor member. The penetration member pierces the end portion in the stacking direction. The penetration member does not include the same kind of material as the charge storage layer.Type: ApplicationFiled: January 11, 2011Publication date: March 15, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Nobutaka WATANABE, Kazuyuki Higashi, Gaku Sudo
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Publication number: 20120028460Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a first conductive member formed on the semiconductor substrate; a first insulating film formed on the same layer as the first conductive member; a second conductive member formed so as to contact with a portion of an upper surface of the first conductive member; a second insulating film formed on the first insulating film so as to contact with a portion of the upper surface of the first conductive member, and including at least one type of element among elements contained in the first insulating film except Si; and an etching stopper film formed on the second insulating film so as to contact with a portion of a side surface of the second conductive member, and having an upper edge located below the upper surface of the second conductive member.Type: ApplicationFiled: October 11, 2011Publication date: February 2, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Makoto WADA, Kazuyuki Higashi
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Patent number: 8058730Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a first conductive member formed on the semiconductor substrate; a first insulating film formed on the same layer as the first conductive member; a second conductive member formed so as to contact with a portion of an upper surface of the first conductive member, a second insulating film formed on the first insulating film so as to contact with a portion of the upper surface of the first conductive member, and including at least one type of element among elements contained in the first insulating film except Si; and an etching stopper film formed on the second insulating film so as to contact with a portion of a side surface of the second conductive member, and having an upper edge located below the upper surface of the second conductive member.Type: GrantFiled: September 26, 2008Date of Patent: November 15, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Makoto Wada, Kazuyuki Higashi
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Publication number: 20110256672Abstract: A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The plurality of first conductive layers comprises a stepped portion formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The wiring comprises a plurality of second conductive layers extending upwardly from an upper surface of the first conductive layers comprising the stepped portion. The plurality of second conductive layers are formed such that upper ends thereof are aligned with a surface parallel to the substrate, and such that a diameter thereof decreases from the upper end thereof to a lower end thereof. The plurality of second conductive layers are formed such that the greater a length thereof in the perpendicular direction, the larger a diameter of the upper end thereof.Type: ApplicationFiled: June 29, 2011Publication date: October 20, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Makoto WADA, Kazuyuki HIGASHI, Naofumi NAKAMURA, Tsuneo UENAKA
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Patent number: 8022461Abstract: A semiconductor device includes a plurality of bit lines repeatedly arranged with a same line width and pitch in a memory device region; a plurality of shunt lines arranged in a same layer as that of the plurality of bit lines, in parallel therewith, and with the same line width and pitch as those of the plurality of bit lines in the memory device region; and an upper-layer contact plug arranged from an upper-layer side so as to be connected to the plurality of shunt lines by extending over two or more shunt lines.Type: GrantFiled: May 19, 2009Date of Patent: September 20, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Makoto Wada, Akihiro Kajita, Kazuyuki Higashi
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Publication number: 20110216597Abstract: A memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The semiconductor layer includes a columnar portion that extends in a perpendicular direction to a substrate. The charge storage layer is formed around a side surface of the columnar portion. The plurality of first conductive layers are formed around the side surface of the columnar portion and the charge storage layer. A control circuit comprises a plurality of second conductive layers, an insulating layer, and a plurality of plug layers. The plurality of second conductive layers are formed in the same layers as the plurality of first conductive layers. The insulating layer is formed penetrating the plurality of second conductive layers in the perpendicular direction. The plurality of plug layers are formed penetrating the insulating layer in the perpendicular direction.Type: ApplicationFiled: September 15, 2010Publication date: September 8, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Kazuyuki HIGASHI, Tadashi Iguchi
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Patent number: 7994054Abstract: A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a first metal film on the insulating film at a second substrate temperature lower than the first substrate temperature, oxidizing at least part of the first metal film with oxidizing species remaining in the insulating film, and forming a second metal film, which includes any of a high melting point metal and a noble metal, on the first metal film, the first metal film and the second metal film sharing different metallic material.Type: GrantFiled: August 30, 2007Date of Patent: August 9, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Atsuko Sakata, Junichi Wada, Seiichi Omoto, Masaaki Hatano, Soichi Yamashita, Kazuyuki Higashi, Naofumi Nakamura, Masaki Yamada, Kazuya Kinoshita, Tomio Katata, Masahiko Hasunuma
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Patent number: 7996813Abstract: A method for generating a pattern includes reading out an interconnect layout and a hole layout, the interconnect layout prescribing interconnect patterns, the hole layout prescribing hole patterns configured to connect to the interconnect patterns; extracting one of the hole patterns to be connected within the same interconnect layer level to one of the interconnect patterns in a pattern processing area; extracting a first processing area including the extracted hole pattern; calculating a first pattern density of the interconnect patterns included in the first processing area; and generating first additional patterns in the first processing area based on the first pattern density.Type: GrantFiled: January 7, 2010Date of Patent: August 9, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Masaaki Hatano, Motoya Okazaki, Junichi Wada, Takeshi Nishioka, Hisashi Kaneko, Takeshi Fujimaki, Kazuyuki Higashi, Kenji Yoshida, Noriaki Matsunaga
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Patent number: 7989880Abstract: A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The plurality of first conductive layers comprises a stepped portion formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The wiring comprises a plurality of second conductive layers extending upwardly from an upper surface of the first conductive layers comprising the stepped portion. The plurality of second conductive layers are formed such that upper ends thereof are aligned with a surface parallel to the substrate, and such that a diameter thereof decreases from the upper end thereof to a lower end thereof. The plurality of second conductive layers are formed such that the greater a length thereof in the perpendicular direction, the larger a diameter of the upper end thereof.Type: GrantFiled: November 10, 2009Date of Patent: August 2, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Makoto Wada, Kazuyuki Higashi, Naofumi Nakamura, Tsuneo Uenaka